Searched refs:PCI_CONF_BASE1 (Results 1 – 19 of 19) sorted by relevance
| /titanic_50/usr/src/uts/sun4u/sys/pci/ |
| H A D | db21554_config.h | 50 #define DB_PCONF_IO_CSR PCI_CONF_BASE1
61 #define DB_SCONF_IO_CSR PCI_CONF_BASE1
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| /titanic_50/usr/src/uts/common/io/igb/ |
| H A D | igb_debug.c | 102 pci_config_get32(handle, PCI_CONF_BASE1)); in pci_dump()
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| /titanic_50/usr/src/uts/common/sys/ |
| H A D | pci.h | 54 #define PCI_CONF_BASE1 0x14 /* base register 1, 4 bytes */ macro
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| /titanic_50/usr/src/uts/common/os/ |
| H A D | sunpci.c | 520 chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1);
874 pci_config_put32(confhdl, PCI_CONF_BASE1, chs_p->chs_base1);
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| /titanic_50/usr/src/uts/common/io/e1000g/ |
| H A D | e1000g_debug.c | 419 pciconfig_bar(Adapter, PCI_CONF_BASE1, "PCI_CONF_BASE1"); in pciconfig_dump()
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| H A D | e1000g_main.c | 738 for (offset = PCI_CONF_BASE1; in e1000g_regs_map()
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| /titanic_50/usr/src/uts/common/io/ixgbe/ |
| H A D | ixgbe_debug.c | 227 pci_config_get32(handle, PCI_CONF_BASE1)); in ixgbe_pci_dump()
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| /titanic_50/usr/src/cmd/pcitool/ |
| H A D | pcitool.c | 276 { PCI_CONF_BASE1, 4, "BAR1", "Base Address Register 1 (@14)" },
288 { PCI_CONF_BASE1, 4, "BAR1", "Base Address Register 1 (@14)" },
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| /titanic_50/usr/src/uts/sun4/io/px/ |
| H A D | px_tools.c | 58 PCI_CONF_BASE1,
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| /titanic_50/usr/src/uts/sun4u/io/pci/ |
| H A D | pci_tools.c | 91 PCI_CONF_BASE1,
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| H A D | db21554.c | 1634 ph->bar1 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE1); in db_pci_get_header()
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| /titanic_50/usr/src/uts/i86pc/io/pci/ |
| H A D | pci_tools.c | 69 PCI_CONF_BASE1,
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| /titanic_50/usr/src/uts/common/io/scsi/adapters/pmcs/ |
| H A D | pmcs_fwlog.c | 753 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE1)); in pmcs_dump_pcie_conf()
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| /titanic_50/usr/src/uts/common/io/fibre-channel/fca/qlge/ |
| H A D | qlge_dbg.c | 667 pci_config_get32(qlge->pci_handle, PCI_CONF_BASE1); in ql_dump_pci_config()
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| /titanic_50/usr/src/uts/common/io/cardbus/ |
| H A D | cardbus_cfg.c | 4362 pci_config_get32(config_handle, PCI_CONF_BASE1));
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| /titanic_50/usr/src/uts/intel/io/hotplug/pcicfg/ |
| H A D | pcicfg.c | 421 pci_config_get32(config_handle, PCI_CONF_BASE1)); in pcicfg_dump_common_config()
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| /titanic_50/usr/src/uts/sun4/io/ |
| H A D | pcicfg.c | 450 pci_config_get32(config_handle, PCI_CONF_BASE1)); in pcicfg_dump_common_config()
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| /titanic_50/usr/src/uts/common/io/fibre-channel/fca/qlc/ |
| H A D | ql_api.c | 15223 chs.chs_base1 = ql_pci_config_get32(ha, PCI_CONF_BASE1); in ql_save_config_regs()
15288 ql_pci_config_put32(ha, PCI_CONF_BASE1, chs_p->chs_base1); in ql_restore_config_regs()
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| H A D | ql_xioctl.c | 1377 chip.MemAddr = ql_pci_config_get32(ha, PCI_CONF_BASE1); in ql_qry_chip()
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