Home
last modified time | relevance | path

Searched refs:PCI_CBUS_MEM_LIMIT1 (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/sys/
H A Dpci.h131 #define PCI_CBUS_MEM_LIMIT1 0x28 /* Memory limit reg 1, 4 bytes */ macro
/titanic_50/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c1524 pci_config_put32(handle, PCI_CBUS_MEM_LIMIT1, 0); in cardbus_setup_bridge()
4451 pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT1));