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Searched refs:PCI_CACHE_LINE_SIZE (Results 1 – 3 of 3) sorted by relevance

/titanic_50/usr/src/uts/sun4u/sys/pci/
H A Dpci_sc.h80 #define PCI_CACHE_LINE_SIZE (PCI_SBUF_LINE_SIZE / 4) macro
/titanic_50/usr/src/uts/sun4u/io/pci/
H A Dpci_util.c588 PCI_CACHE_LINE_SIZE); in init_child()
/titanic_50/usr/src/uts/common/io/cardbus/
H A Dcardbus.c1169 PCI_CACHE_LINE_SIZE); in cardbus_init_child_regs()