Home
last modified time | relevance | path

Searched refs:PCICFG_CACHE_LINE_SIZE (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dpcics_reg_driver.h23 #define PCICFG_CACHE_LINE_SIZE 0x0c macro
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_devinfo.c316 lm_status = mm_read_pci(pdev, PCICFG_CACHE_LINE_SIZE, &val); in lm_get_pcicfg_info()