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Searched refs:NLP2020_GPIO_CTL_REG (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/sys/nxge/
H A Dnxge_phy_hw.h959 #define NLP2020_GPIO_CTL_REG 0xC108 macro
/titanic_50/usr/src/uts/common/io/nxge/
H A Dnxge_mac.c3560 NLP2020_GPIO_ADDR, NLP2020_GPIO_CTL_REG, in nxge_nlp2020_xcvr_init()
3565 NLP2020_GPIO_ADDR, NLP2020_GPIO_CTL_REG, in nxge_nlp2020_xcvr_init()
7457 NLP2020_GPIO_ADDR, NLP2020_GPIO_CTL_REG, 0xb000); in nxge_check_nlp2020_link()
7464 NLP2020_GPIO_ADDR, NLP2020_GPIO_CTL_REG, 0xd000); in nxge_check_nlp2020_link()