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Searched refs:NLP2020_CL45_PORT0_ADDR1 (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/sys/nxge/
H A Dnxge_phy_hw.h116 #define NLP2020_CL45_PORT0_ADDR1 0x12 macro
/titanic_50/usr/src/uts/common/io/nxge/
H A Dnxge_mac.c7530 } else if (nxge_is_phy_present(nxgep, NLP2020_CL45_PORT0_ADDR1, in nxge_hswap_phy_present()
7532 nxgep->xcvr_addr = NLP2020_CL45_PORT0_ADDR1; in nxge_hswap_phy_present()
8198 case NLP2020_CL45_PORT0_ADDR1: in nxge_scan_ports_phy()
8229 case NLP2020_CL45_PORT0_ADDR1: in nxge_scan_ports_phy()