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Searched refs:MSG_REC (Results 1 – 7 of 7) sorted by relevance

/titanic_50/usr/src/uts/sun4/io/px/
H A Dpx_pec.c164 MSG_REC, (msgcode_t)PCIE_CORR_MSG, -1, in px_pec_msg_add_intr()
176 PX_ERR_LOW_PIL, PX_INTR_STATE_ENABLE, MSG_REC, in px_pec_msg_add_intr()
187 MSG_REC, (msgcode_t)PCIE_NONFATAL_MSG, -1, in px_pec_msg_add_intr()
200 PX_ERR_PIL, PX_INTR_STATE_ENABLE, MSG_REC, in px_pec_msg_add_intr()
211 MSG_REC, (msgcode_t)PCIE_FATAL_MSG, -1, in px_pec_msg_add_intr()
223 PX_INTR_STATE_ENABLE, MSG_REC, PCIE_FATAL_MSG)) != DDI_SUCCESS) { in px_pec_msg_add_intr()
259 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, in px_pec_msg_rem_intr()
264 PX_ERR_LOW_PIL, PX_INTR_STATE_DISABLE, MSG_REC, in px_pec_msg_rem_intr()
276 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, in px_pec_msg_rem_intr()
281 PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, in px_pec_msg_rem_intr()
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H A Dpx_ioapi.h511 MSG_REC = (uint32_t)1, /* PCIe message record */ enumerator
H A Dpx.c650 if (px_add_msiq_intr(dip, dip, &hdl, MSG_REC, in px_pwr_setup()
662 PX_INTR_STATE_ENABLE, MSG_REC, PCIE_PME_ACK_MSG) != DDI_SUCCESS) { in px_pwr_setup()
672 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, in px_pwr_setup()
702 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, in px_pwr_teardown()
707 PX_INTR_STATE_DISABLE, MSG_REC, PCIE_PME_ACK_MSG); in px_pwr_teardown()
H A Dpx_msiq.c159 if (rec_type == MSG_REC) { in px_msiq_alloc()
241 if (rec_type == MSG_REC) { in px_msiq_alloc_based_on_cpuid()
H A Dpx_intr.c324 case MSG_REC: in px_msiq_intr()
378 if ((rec_type == MSG_REC) && in px_msiq_intr()
/titanic_50/usr/src/cmd/mdb/sparc/modules/intr/
H A Dintr.c425 if (ih.ih_rec_type != MSG_REC) { in intr_px_print_items()
/titanic_50/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.c1035 msiq_rec_p->msiq_rec_type = MSG_REC; in px_lib_get_msiq_rec()