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Searched refs:MII_TG3_DSP_RW_PORT (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/grub/grub-0.97/netboot/
H A Dtg3.c252 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_writedsp()
335 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
361 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low); in tg3_phy_write_and_check_testpat()
362 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high); in tg3_phy_write_and_check_testpat()
372 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
373 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
394 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
438 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800); in tg3_phy_reset_5703_4_5()
450 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000); in tg3_phy_reset_5703_4_5()
2510 tg3_writedsp(tp, MII_TG3_DSP_RW_PORT, 0x2aaa); in tg3_phy_probe()
H A Dtg3.h1592 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ macro