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Searched refs:MII_CONTROL (Results 1 – 18 of 18) sorted by relevance

/titanic_50/usr/src/uts/common/io/nge/
H A Dnge_xmii.c211 control = nge_mii_get16(ngep, MII_CONTROL); in nge_phy_recover()
213 nge_mii_put16(ngep, MII_CONTROL, control); in nge_phy_recover()
216 control = nge_mii_get16(ngep, MII_CONTROL); in nge_phy_recover()
242 control = nge_mii_get16(ngep, MII_CONTROL); in nge_phy_reset()
244 nge_mii_put16(ngep, MII_CONTROL, control); in nge_phy_reset()
249 control = nge_mii_get16(ngep, MII_CONTROL); in nge_phy_reset()
465 nge_mii_put16(ngep, MII_CONTROL, control); in nge_update_copper()
474 control = nge_mii_get16(ngep, MII_CONTROL); in nge_update_copper()
476 nge_mii_put16(ngep, MII_CONTROL, control); in nge_update_copper()
/titanic_50/usr/src/uts/intel/io/dnet/
H A Ddnet_mii.c124 mac->mii_read(dip, phy, MII_CONTROL); in mii_probe_phy()
127 mac->mii_read(dip, phy, MII_CONTROL), status); in mii_probe_phy()
301 mac->mii_write(mac->mii_dip, phy, MII_CONTROL, in mii_reset_phy()
313 control = mac->mii_read(mac->mii_dip, phy, MII_CONTROL); in mii_reset_phy()
324 control = mac->mii_read(mac->mii_dip, phy, MII_CONTROL); in mii_reset_phy()
386 mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control); in mii_sync()
455 mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control); in mii_autoneg_enab()
541 mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control); in mii_fixspeed()
559 mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control); in mii_isolate()
575 mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control); in mii_unisolate()
[all …]
/titanic_50/usr/src/uts/common/io/atge/
H A Datge_mii.c198 atge_mii_write(atgep, phyaddr, MII_CONTROL, MII_CONTROL_RESET); in atge_l1_mii_reset()
223 atge_mii_write(atgep, phyaddr, MII_CONTROL, in atge_l1_mii_reset()
370 if (reg == MII_CONTROL) { in atge_l1c_mii_write()
/titanic_50/usr/src/uts/common/io/mii/
H A Dmii.c1086 PHY_CLR(ph, MII_CONTROL, in phy_reset()
1092 PHY_SET(ph, MII_CONTROL, MII_CONTROL_RESET); in phy_reset()
1111 if ((phy_read(ph, MII_CONTROL) & MII_CONTROL_RESET) == 0) { in phy_reset()
1124 phy_write(ph, MII_CONTROL, MII_CONTROL_ISOLATE); in phy_stop()
1204 phy_write(ph, MII_CONTROL, bmcr); in phy_loop()
1266 PHY_SET(ph, MII_CONTROL, MII_CONTROL_PWRDN); in phy_start()
1355 phy_write(ph, MII_CONTROL, bmcr & ~(MII_CONTROL_RSAN)); in phy_start()
1368 phy_write(ph, MII_CONTROL, bmcr); in phy_start()
1384 control = phy_read(ph, MII_CONTROL); in phy_check()
H A Dmii_marvell.c193 reg = phy_read(ph, MII_CONTROL); in mvphy_loop_88e3016()
195 phy_write(ph, MII_CONTROL, reg); in mvphy_loop_88e3016()
/titanic_50/usr/src/uts/common/sys/
H A Dmiiregs.h38 #define MII_CONTROL 0 macro
/titanic_50/usr/src/grub/grub-0.97/netboot/
H A Dsis900.h239 MII_CONTROL = 0x0000, enumerator
H A Dsis900.c863 if(sis900_mdio_read(phy_addr, MII_CONTROL) & MII_CNTL_FDX) in sis900_read_mode()
/titanic_50/usr/src/uts/common/io/bge/
H A Dbge_mii.c252 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET); in bge_phy_reset()
255 control = bge_mii_get16(bgep, MII_CONTROL); in bge_phy_reset()
277 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_PWRDN); in bge_phy_powerdown()
1090 bge_mii_put16(bgep, MII_CONTROL, control); in bge_update_copper()
H A Dbge_kstats.c498 { MII_CONTROL, "mii_control" },
/titanic_50/usr/src/uts/common/io/bfe/
H A Dbfe.c376 bfe_write_phy(bfe, MII_CONTROL, MII_CONTROL_RESET); in bfe_reset_phy()
379 if (bfe_read_phy(bfe, MII_CONTROL) & in bfe_reset_phy()
418 bfe_write_phy(bfe, MII_CONTROL, MII_CONTROL_PWRDN | in bfe_stop_phy()
443 bfe_write_phy(bfe, MII_CONTROL, 0); in bfe_probe_phy()
452 bfe_write_phy(bfe, MII_CONTROL, 0); in bfe_probe_phy()
698 bfe_write_phy(bfe, MII_CONTROL, bmcr); in bfe_startup_phy()
742 bmcr = bfe_read_phy(bfe, MII_CONTROL); in bfe_check_link()
/titanic_50/usr/src/uts/common/io/sfe/
H A Dsfe_util.c2294 val = gem_mii_read(dp, MII_CONTROL); in gem_mii_link_check()
2305 gem_mii_write(dp, MII_CONTROL, 0); in gem_mii_link_check()
2543 val = gem_mii_read(dp, MII_CONTROL); in gem_mii_link_check()
2589 val = gem_mii_read(dp, MII_CONTROL); in gem_mii_link_check()
2619 gem_mii_write(dp, MII_CONTROL, val); in gem_mii_link_check()
2785 gem_mii_write(dp, MII_CONTROL, MII_CONTROL_RESET); in gem_mii_link_check()
2798 val = gem_mii_read(dp, MII_CONTROL) & in gem_mii_link_check()
2801 gem_mii_write(dp, MII_CONTROL, in gem_mii_link_check()
2873 gem_mii_write(dp, MII_CONTROL, 0); in gem_mii_probe_default()
2895 gem_mii_write(dp, MII_CONTROL, 0); in gem_mii_probe_default()
[all …]
/titanic_50/usr/src/uts/common/io/mxfe/
H A Dmxfe.c975 mxfe_miiwrite(mxfep, mxfep->mxfe_phyaddr, MII_CONTROL, in mxfe_stopphy()
1314 mxfe_miiwrite(mxfep, phyaddr, MII_CONTROL, MII_CONTROL_RESET); in mxfe_startphymii()
1321 if (mxfe_miiread(mxfep, phyaddr, MII_CONTROL) & in mxfe_startphymii()
1336 bmcr = mxfe_miiread(mxfep, phyaddr, MII_CONTROL); in mxfe_startphymii()
1424 mxfe_miiwrite(mxfep, phyaddr, MII_CONTROL, bmcr); in mxfe_startphymii()
1491 bmcr = mxfe_miiread(mxfep, mxfep->mxfe_phyaddr, MII_CONTROL); in mxfe_checklinkmii()
/titanic_50/usr/src/uts/common/io/rge/
H A Drge_chip.c360 control = rge_mii_get16(rgep, MII_CONTROL); in rge_phy_reset()
361 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET); in rge_phy_reset()
364 control = rge_mii_get16(rgep, MII_CONTROL); in rge_phy_reset()
574 rge_mii_put16(rgep, MII_CONTROL, control); in rge_phy_update()
/titanic_50/usr/src/uts/common/io/rtls/
H A Drtls.c1925 case MII_CONTROL: in rtls_mii_read()
1967 case MII_CONTROL: in rtls_mii_write()
/titanic_50/usr/src/uts/common/io/afe/
H A Dafe.c1253 case MII_CONTROL: in afe_miireadcomet()
1350 case MII_CONTROL: in afe_miiwritecomet()
/titanic_50/usr/src/uts/common/io/vr/
H A Dvr.c2703 vr_phy_write(vrp, MII_CONTROL, vrp->chip.mii.control); in vr_link_init()
2727 vr_phy_read(vrp, MII_CONTROL, &vrp->chip.mii.control); in vr_link_state()
/titanic_50/usr/src/uts/common/io/nxge/npi/
H A Dnpi_mac.c3294 case MII_CONTROL: in npi_mac_pcs_mii_read()
3373 case MII_CONTROL: in npi_mac_pcs_mii_write()