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Searched refs:MDIO_WC_REG_XGXSBLK1_LANETEST0 (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc_reg.h546 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a macro
/titanic_50/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c5006 MDIO_WC_REG_XGXSBLK1_LANETEST0, 0); in elink_warpcore_powerdown_secondport_lanes()