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Searched refs:MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc_reg.h617 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec macro
/titanic_50/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c5180 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, in elink_warpcore_set_quad_mode()
5183 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, in elink_warpcore_set_quad_mode()
5215 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, in elink_warpcore_set_dual_mode()
5218 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, in elink_warpcore_set_dual_mode()