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Searched refs:MDIO_PMA_REG_CTRL (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc_reg.h299 #define MDIO_PMA_REG_CTRL 0x0 macro
/titanic_50/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c6678 MDIO_PMA_REG_CTRL, &ctrl); in elink_wait_reset_complete()
6683 MDIO_PMA_REG_CTRL, &ctrl); in elink_wait_reset_complete()
8046 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); in elink_807x_force_10G()
8439 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in elink_8705_config_init()
9763 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in elink_8706_config_init()
9872 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); in elink_8726_config_loopback()
9941 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in elink_8726_config_init()
9956 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); in elink_8726_config_init()
10109 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); in elink_8727_config_speed()
10149 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); in elink_8727_config_speed()
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