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Searched refs:MAX_SAD_DRAM_RULE (Results 1 – 3 of 3) sorted by relevance

/titanic_50/usr/src/uts/intel/io/intel_nhm/
H A Dmem_addr.h60 extern sad_t sad[MAX_SAD_DRAM_RULE];
H A Dmem_addr.c42 sad_t sad[MAX_SAD_DRAM_RULE];
125 for (i = 0; i < MAX_SAD_DRAM_RULE; i++) { in address_to_node()
345 for (i = 0; i < MAX_SAD_DRAM_RULE; i++) { in socket_interleave()
919 for (i = 0; i < MAX_SAD_DRAM_RULE; i++) { in mem_reg_init()
H A Dintel_nhm.h235 #define MAX_SAD_DRAM_RULE 8 macro