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Searched refs:MAX_CORES_PER_CMP (Results 1 – 14 of 14) sorted by relevance

/titanic_50/usr/src/uts/i86pc/sys/
H A Ddrmach.h52 #define MAX_CORES_PER_CMP drmach_max_core_per_cmp() macro
55 #define MAX_CPU_UNITS_PER_BOARD (MAX_CMP_UNITS_PER_BOARD * MAX_CORES_PER_CMP)
58 #define CPU_IMPL_IS_CMP(impl) (MAX_CORES_PER_CMP > 1)
H A Ddr.h108 (DEVSET_BIX(t) + (u) * MAX_CORES_PER_CMP) : DEVSET_BIX(t) + (u))
118 #define DEVSET_CMP_NMASK ((dr_devset_t)((1ULL << MAX_CORES_PER_CMP) - 1))
221 #define DR_CMP_CORE_UNUM(cmp, core) ((cmp) * MAX_CORES_PER_CMP + (core))
228 ((d) == SBD_COMP_CPU ? ((n) / MAX_CORES_PER_CMP) : \
229 (d) == SBD_COMP_CMP ? ((n) / MAX_CORES_PER_CMP) : (n))
/titanic_50/usr/src/uts/i86pc/io/dr/
H A Ddr_cpu.c239 if ((up->sbc_cm.sbdev_unum % MAX_CORES_PER_CMP) == 0) { in dr_pre_attach_cpu()
504 if ((up->sbc_cm.sbdev_unum % MAX_CORES_PER_CMP) == 0) { in dr_pre_detach_cpu()
714 cstat = kmem_zalloc(sizeof (sbd_cpu_stat_t) * MAX_CORES_PER_CMP, in dr_cpu_status()
735 for (core = 0; core < MAX_CORES_PER_CMP; core++) { in dr_cpu_status()
791 kmem_free(cstat, sizeof (sbd_cpu_stat_t) * MAX_CORES_PER_CMP); in dr_cpu_status()
H A Ddr.c1619 for (core = 1; core < MAX_CORES_PER_CMP; core++) { in dr_dev_make_list()
/titanic_50/usr/src/uts/sun4u/starcat/sys/
H A Ddrmach.h55 #define MAX_CORES_PER_CMP 2 macro
/titanic_50/usr/src/uts/sun4u/starfire/sys/
H A Ddrmach.h48 #define MAX_CORES_PER_CMP 1 macro
/titanic_50/usr/src/uts/sun4u/opl/sys/
H A Ddrmach.h57 #define MAX_CORES_PER_CMP OPL_MAX_CPU_PER_CMP macro
/titanic_50/usr/src/uts/sun4u/ngdr/io/
H A Ddr_cpu.c776 sbd_cpu_stat_t cstat[MAX_CORES_PER_CMP]; in dr_cpu_status()
803 for (core = 0; core < MAX_CORES_PER_CMP; core++) { in dr_cpu_status()
H A Ddr.c1650 for (core = 1; core < MAX_CORES_PER_CMP; core++) { in dr_dev_make_list()
/titanic_50/usr/src/uts/sun4u/io/
H A Dsbd_cpu.c241 sbd_cpu_stat_t cstat[MAX_CORES_PER_CMP]; in sbd_cpu_flags()
284 for (core = 0; core < MAX_CORES_PER_CMP; core++) { in sbd_cpu_flags()
H A Dsbd.c2857 nunits = MAX_CORES_PER_CMP; in sbd_get_devlist()
/titanic_50/usr/src/uts/sun4u/sys/
H A Dsbdpriv.h614 #define MAX_CORES_PER_CMP 2 macro
/titanic_50/usr/src/uts/i86pc/io/acpi/drmach_acpi/
H A Ddrmach_acpi.c898 } else if (!ISP2(MAX_CORES_PER_CMP)) { in drmach_init()
901 MAX_CORES_PER_CMP); in drmach_init()
/titanic_50/usr/src/uts/sun4u/starcat/io/
H A Ddrmach.c4976 drmach_device_t *dp[MAX_CORES_PER_CMP]; in drmach_board_test()
4983 cpu_flag_t oflags[MAX_CORES_PER_CMP]; in drmach_board_test()
5077 for (i = 0; i < MAX_CORES_PER_CMP; i++) { in drmach_board_test()
7556 for (curr = 0; curr < MAX_CORES_PER_CMP; curr++) { in drmach_iocage_cmp_acquire()