Home
last modified time | relevance | path

Searched refs:IXGBE_RDRXCTL (Results 1 – 5 of 5) sorted by relevance

/titanic_50/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_dcb_82598.c152 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); in ixgbe_dcb_config_rx_arbiter_82598()
156 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); in ixgbe_dcb_config_rx_arbiter_82598()
H A Dixgbe_x550.c915 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); in ixgbe_disable_mdd_X550()
917 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); in ixgbe_disable_mdd_X550()
938 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); in ixgbe_enable_mdd_X550()
940 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); in ixgbe_enable_mdd_X550()
H A Dixgbe_type.h347 #define IXGBE_RDRXCTL 0x02F00 macro
/titanic_50/usr/src/uts/common/io/ixgbe/
H A Dixgbe_debug.c473 reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); in ixgbe_dump_regs()
H A Dixgbe_main.c2370 reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); in ixgbe_setup_rx_ring()
2372 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg_val); in ixgbe_setup_rx_ring()
2553 reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); in ixgbe_setup_rx()
2558 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg_val); in ixgbe_setup_rx()