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Searched refs:INTR_IDLE_STATE (Results 1 – 8 of 8) sorted by relevance

/titanic_50/usr/src/uts/sun4/io/px/
H A Dpx_ioapi.h73 INTR_IDLE_STATE = (uint32_t)0, enumerator
H A Dpx_ib.c137 px_lib_intr_setstate(px_p->px_dip, sysino, INTR_IDLE_STATE); in px_ib_intr_enable()
643 ret = px_lib_intr_setstate(dip, sysino, INTR_IDLE_STATE); in px_ib_ino_add_intr()
709 ret = px_lib_intr_setstate(dip, sysino, INTR_IDLE_STATE); in px_ib_ino_rem_intr()
H A Dpx_intr.c115 INTR_IDLE_STATE) != DDI_SUCCESS) in px_spurintr()
220 ino_p->ino_sysino, INTR_IDLE_STATE) != DDI_SUCCESS) in px_intx_intr()
458 INTR_IDLE_STATE) != DDI_SUCCESS) in px_msiq_intr()
/titanic_50/usr/src/uts/sun4u/io/px/
H A Dpx_hlib.c2118 *intr_state = INTR_IDLE_STATE; in hvio_intr_getstate()
2148 case INTR_IDLE_STATE: in hvio_intr_setstate()
2790 if ((ret = hvio_intr_setstate(dev_hdl, sysino, INTR_IDLE_STATE)) in hvio_resume()
2899 if ((ret = hvio_intr_setstate(pci_dev_hdl, sysino, INTR_IDLE_STATE)) in hvio_cb_resume()
H A Dpx_lib4u.c498 INTR_IDLE_STATE) != DDI_SUCCESS) in px_lib_intr_reset()
2313 INTR_IDLE_STATE); in px_cb_rem_intr()
2559 pxu_p->hp_sysino, INTR_IDLE_STATE) != DDI_SUCCESS) in px_hp_intr()
H A Dpx_err.c668 INTR_IDLE_STATE); in px_err_cb_intr()
714 INTR_IDLE_STATE); in px_err_dmc_pec_intr()
/titanic_50/usr/src/uts/sun4v/io/px/
H A Dpx_err.c306 INTR_IDLE_STATE) != DDI_SUCCESS) { in px_err_intr()
H A Dpx_lib4v.c418 INTR_IDLE_STATE) != DDI_SUCCESS) in px_lib_intr_reset()