Searched refs:INT0 (Results 1 – 2 of 2) sorted by relevance
| /titanic_50/usr/src/uts/intel/io/amd8111s/ |
| H A D | amd8111s_hw.c | 260 data32 = READ_REG32(pLayerPointers, MemBaseAddress + INT0); in mdlClearHWConfig()
261 WRITE_REG32(pLayerPointers, MemBaseAddress + INT0, data32); in mdlClearHWConfig()
454 nINT0 = READ_REG32(pLayerPointers, pMdl->Mem_Address + INT0); in mdlReadInterrupt()
457 WRITE_REG32(pLayerPointers, pMdl->Mem_Address + INT0, nINT0); in mdlReadInterrupt()
823 nINT0 = READ_REG32(pLayerPointers, pMdl->Mem_Address + INT0); in mdlStopChip()
824 WRITE_REG32(pLayerPointers, pMdl->Mem_Address + INT0, nINT0); in mdlStopChip()
865 nINT0 = READ_REG32(pLayerPointers, pMdl->Mem_Address + INT0); in mdlClearInterrupt()
866 WRITE_REG32(pLayerPointers, pMdl->Mem_Address + INT0, nINT0); in mdlClearInterrupt()
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| H A D | amd8111s_hw.h | 297 #define INT0 0x38 /* 32bit register */ macro
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