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Searched refs:HXGE_REG_WR64 (Results 1 – 9 of 9) sorted by relevance

/titanic_50/usr/src/uts/common/io/hxge/
H A Dhpi_vmac.c43 HXGE_REG_WR64(handle, VMAC_RST, reset.value); in hpi_tx_vmac_reset()
57 HXGE_REG_WR64(handle, VMAC_RST, reset.value); in hpi_rx_vmac_reset()
123 HXGE_REG_WR64(handle, VMAC_TX_CFG, cfg.value); in hpi_vmac_tx_config()
147 HXGE_REG_WR64(handle, VMAC_RX_CFG, cfg.value); in hpi_vmac_rx_set_framesize()
240 HXGE_REG_WR64(handle, VMAC_RX_CFG, cfg.value); in hpi_vmac_rx_config()
H A Dhpi_txdma.h58 HXGE_REG_WR64(handle, \
H A Dhxge_txdma.c2101 HXGE_REG_WR64(hxgep->hpi_handle, TDC_FIFO_ERR_STAT, 0x7); in hxge_txdma_hw_start()
2106 HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_DATA_HI, 0x0ULL); in hxge_txdma_hw_start()
2107 HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_DATA_LO, 0x0ULL); in hxge_txdma_hw_start()
2110 HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_CMD, in hxge_txdma_hw_start()
2117 HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_CMD, tmp); in hxge_txdma_hw_start()
2134 HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_CMD, tmp); in hxge_txdma_hw_start()
2182 HXGE_REG_WR64(hxgep->hpi_handle, TDC_FIFO_ERR_STAT, 0x7); in hxge_txdma_hw_start()
2183 HXGE_REG_WR64(hxgep->hpi_handle, TDC_FIFO_ERR_MASK, 0x0); in hxge_txdma_hw_start()
2682 HXGE_REG_WR64(handle, TDC_FIFO_ERR_STAT, fifo_stat.value); in hxge_txdma_handle_sys_errors()
H A Dhpi_rxdma.h120 HXGE_REG_WR64(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
H A Dhxge_common_impl.h219 #define HXGE_REG_WR64(handle, offset, val) { \ macro
H A Dhxge_rxdma.c3202 HXGE_REG_WR64(hxgep->hpi_handle, RDC_PREF_CMD, i); in hxge_rxdma_hw_start()
3209 HXGE_REG_WR64(hxgep->hpi_handle, RDC_SHADOW_CMD, i); in hxge_rxdma_hw_start()
3216 HXGE_REG_WR64(hxgep->hpi_handle, RDC_CTRL_FIFO_CMD, i); in hxge_rxdma_hw_start()
3223 HXGE_REG_WR64(hxgep->hpi_handle, RDC_DATA_FIFO_CMD, i); in hxge_rxdma_hw_start()
3229 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_STAT, 0xFF); in hxge_rxdma_hw_start()
3232 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); in hxge_rxdma_hw_start()
3525 HXGE_REG_WR64(handle, RDC_FIFO_ERR_STAT, stat.value); in hxge_rxdma_handle_sys_errors()
3805 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); in hxge_rx_port_fatal_err_recover()
H A Dhxge_pfc.h51 HXGE_REG_WR64((handle), (offset), (value))
H A Dhpi_txdma.c372 HXGE_REG_WR64(handle, offset, 0); in hpi_txdma_desc_set_zero()
H A Dhpi_rxdma.c481 HXGE_REG_WR64(handle, offset, clk_div.value); in hpi_rxdma_cfg_clock_div_set()