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Searched refs:HWS_PGA (Results 1 – 4 of 4) sorted by relevance

/titanic_50/usr/src/uts/intel/io/drm/
H A Di915_dma.c102 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); in i915_init_hardware_status()
103 (void) I915_READ(HWS_PGA); in i915_init_hardware_status()
118 I915_WRITE(HWS_PGA, 0x1ffff000); in i915_free_hardware_status()
125 I915_WRITE(HWS_PGA, 0x1ffff000); in i915_free_hardware_status()
255 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); in i915_dma_resume()
257 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); in i915_dma_resume()
899 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); in i915_set_status_page()
H A Di915_drv.c693 S3_WRITE(HWS_PGA, s3_priv->saveHWS); in i915_resume()
695 (void) S3_READ(HWS_PGA); in i915_resume()
747 s3_priv->saveHWS = S3_READ(HWS_PGA); in i915_suspend()
H A Di915_gem.c2688 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); in i915_gem_init_hws()
2689 (void) I915_READ(HWS_PGA); /* posting read */ in i915_gem_init_hws()
2715 I915_WRITE(HWS_PGA, 0x1ffff000); in i915_gem_cleanup_hws()
H A Di915_drv.h748 #define HWS_PGA 0x02080 macro