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Searched refs:GRCBASE_MISC (Results 1 – 5 of 5) sorted by relevance

/titanic_50/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dgrc_addr.h17 #define GRCBASE_MISC 0x00A000 macro
59 #define GRCBASE_MISC_AEU GRCBASE_MISC // just for driver init
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_er.c189 REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in lm_er_process_kill_chip_reset()
192 REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in lm_er_process_kill_chip_reset()
195 REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2); in lm_er_process_kill_chip_reset()
197 REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); in lm_er_process_kill_chip_reset()
H A Dlm_hw_init_reset.c632 … REG_WR(pdev,(GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET),MISC_REGISTERS_RESET_REG_1_RST_RBCP); in rbc_reset_workaround()
746 REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_1_CLEAR, reg_1_clear ); in lm_reset_path()
756 REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_2_CLEAR, reg_2_clear); in lm_reset_path()
762 … REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_1_SET, MISC_REGISTERS_RESET_REG_1_RST_NIG); in lm_reset_path()
2564 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,reset_reg_1_val); in init_misc_common()
2566 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_2_SET,reset_reg_2_val); in init_misc_common()
3856 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_CLEAR,0x3); in prs_brb_mem_setup()
3858 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,0x3); in prs_brb_mem_setup()
3933 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_CLEAR,0x03); in prs_brb_mem_setup()
3935 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,0x03); in prs_brb_mem_setup()
[all …]
H A Dlm_mcp.c246 REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_2_CLEAR, in lm_reset_mcp()
/titanic_50/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c1674 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in elink_emac_init()
1677 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in elink_emac_init()
1750 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in elink_umac_enable()
1754 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in elink_umac_enable()
1865 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in elink_xmac_init()
1869 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in elink_xmac_init()
1895 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in elink_xmac_init()
1899 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in elink_xmac_init()
2015 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in elink_emac_enable()
2165 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in elink_emac_enable()
[all …]