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Searched refs:F_BUSY (Results 1 – 5 of 5) sorted by relevance

/titanic_50/usr/src/uts/common/io/chxge/com/
H A Dmc4.c71 if (!(t1_read_reg_4(adapter, addr) & F_BUSY)) in wrreg_wait()
177 } while ((val & F_BUSY) && --attempts); in t1_mc4_init()
178 if (val & F_BUSY) { in t1_mc4_init()
314 while ((val & F_BUSY) && attempts--) in t1_mc4_bd_read()
317 if (val & F_BUSY) in t1_mc4_bd_read()
H A Dmc3.c186 if (!(t1_read_reg_4(adapter, addr) & F_BUSY)) in wrreg_wait()
313 } while ((val & F_BUSY) && --attempts); in t1_mc3_init()
314 if (val & F_BUSY) { in t1_mc3_init()
H A Dregs.h323 #define F_BUSY V_BUSY(1U) macro
/titanic_50/usr/src/uts/common/io/cxgbe/common/
H A Dt4_hw.c720 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) in sf1_read()
724 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); in sf1_read()
748 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) in sf1_write()
753 return (t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5)); in sf1_write()
3672 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) in t4_wol_pat_enable()
3679 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) in t4_wol_pat_enable()
3838 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); in t4_sge_ctxt_rd_bd()
H A Dt4_regs.h1424 #define F_BUSY V_BUSY(1U) macro