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Searched refs:EnableMask (Results 1 – 3 of 3) sorted by relevance

/titanic_50/usr/src/uts/intel/io/acpica/hardware/
H A Dhwgpe.c63 UINT8 EnableMask,
112 UINT32 EnableMask; in AcpiHwLowSetGpe() local
129 Status = AcpiHwRead (&EnableMask, &GpeRegisterInfo->EnableAddress); in AcpiHwLowSetGpe()
144 if (!(RegisterBit & GpeRegisterInfo->EnableMask)) in AcpiHwLowSetGpe()
153 ACPI_SET_BIT (EnableMask, RegisterBit); in AcpiHwLowSetGpe()
158 ACPI_CLEAR_BIT (EnableMask, RegisterBit); in AcpiHwLowSetGpe()
169 Status = AcpiHwWrite (EnableMask, &GpeRegisterInfo->EnableAddress); in AcpiHwLowSetGpe()
327 UINT8 EnableMask, in AcpiHwGpeEnableWrite() argument
333 GpeRegisterInfo->EnableMask = EnableMask; in AcpiHwGpeEnableWrite()
335 Status = AcpiHwWrite (EnableMask, &GpeRegisterInfo->EnableAddress); in AcpiHwGpeEnableWrite()
/titanic_50/usr/src/uts/intel/io/acpica/events/
H A Devgpe.c108 GpeRegisterInfo->EnableMask = GpeRegisterInfo->EnableForRun; in AcpiEvUpdateGpeEnableMask()
/titanic_50/usr/src/uts/intel/sys/acpi/
H A Daclocal.h570 UINT8 EnableMask; /* Current mask of enabled GPEs */ member