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Searched refs:E1000_PHY_CTRL (Results 1 – 3 of 3) sorted by relevance

/titanic_50/usr/src/uts/common/io/e1000api/
H A De1000_regs.h108 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ macro
109 #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
H A De1000_ich8lan.c2543 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_oem_bits_config_ich8lan()
3217 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_set_d0_lplu_state_ich8lan()
3221 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3246 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3310 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_set_d3_lplu_state_ich8lan()
3314 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
3355 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
5476 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_kmrn_lock_loss_workaround_ich8lan()
5479 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_kmrn_lock_loss_workaround_ich8lan()
5539 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_igp3_phy_powerdown_workaround_ich8lan()
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H A De1000_phy.c3440 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) in e1000_access_phy_wakeup_reg_bm()