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Searched refs:DEBUG2 (Results 1 – 25 of 30) sorted by relevance

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/titanic_50/usr/src/uts/sun4u/io/pci/
H A Dpci_util.c84 DEBUG2(DBG_ATTACH, dip, "get_pci_properties: bus-range (%x,%x)\n", in get_pci_properties()
366 DEBUG2(DBG_CTLOPS, pci_p->pci_dip, in uninit_child()
511 DEBUG2(DBG_PWR, ddi_get_parent(child), in init_child()
540 DEBUG2(DBG_INIT_CLD, pci_p->pci_dip, "%s: header_type=%x\n", in init_child()
555 DEBUG2(DBG_INIT_CLD, pci_p->pci_dip, "%s: command-preserve=%x\n", in init_child()
562 DEBUG2(DBG_INIT_CLD, pci_p->pci_dip, "%s: command=%x\n", in init_child()
609 DEBUG2(DBG_INIT_CLD, pci_p->pci_dip, "%s: min_gnt=%x\n", in init_child()
821 DEBUG2(DBG_DETACH, dip, "DDI_SUSPEND: skipping " in pci_child_cfg_save()
873 DEBUG2(DBG_DETACH, dip, in pci_child_cfg_restore()
886 DEBUG2(DBG_PWR, dip, in pci_child_cfg_restore()
H A Dpci_iommu.c119 DEBUG2(DBG_ATTACH, dip, "iommu_create: ctrl=%p, tsb=%p\n", in iommu_create()
121 DEBUG2(DBG_ATTACH, dip, "iommu_create: page_flush=%p, ctx_flush=%p\n", in iommu_create()
123 DEBUG2(DBG_ATTACH, dip, "iommu_create: tsb vaddr=%p tsb_paddr=%p\n", in iommu_create()
127 DEBUG2(DBG_ATTACH, dip, "iommu_create: fast tsb tte addr: %x + %x\n", in iommu_create()
134 DEBUG2(DBG_ATTACH, dip, in iommu_create()
238 DEBUG2(DBG_ATTACH, dip, "iommu_configure: iommu_ctl=%08x.%08x\n", in iommu_configure()
391 DEBUG2(DBG_UNMAP_WIN, dip, "mp=%p %x pfns:", mp, npages); in iommu_unmap_window()
H A Dpci_pwr.c86 DEBUG2(DBG_PWR, ddi_get_parent(dip), "ADDING NEW PWR_INFO %s@%s\n", in pci_pwr_create_info()
560 DEBUG2(DBG_DETACH, dip, in pci_pwr_resume()
574 DEBUG2(DBG_PWR, dip, in pci_pwr_resume()
611 DEBUG2(DBG_DETACH, dip, "DDI_SUSPEND: skipping " in pci_pwr_suspend()
732 DEBUG2(DBG_PWR, pwr_p->pwr_dip, in pci_pwr_change()
742 DEBUG2(DBG_PWR, pwr_p->pwr_dip, in pci_pwr_change()
751 DEBUG2(DBG_PWR, pwr_p->pwr_dip, "pwr_change: " in pci_pwr_change()
H A Dpci_sc.c73 DEBUG2(DBG_ATTACH, dip, "sc_create: ctx_invl=%x ctx_match=%x\n", in sc_create()
94 DEBUG2(DBG_ATTACH, dip, "sc_create: sync buffer - vaddr=%x paddr=%x\n", in sc_create()
H A Dpci_devctl.c104 DEBUG2(DBG_OPEN, pci_p->pci_dip, "devp=%x: flags=%x\n", devp, flags); in pci_open()
151 DEBUG2(DBG_CLOSE, pci_p->pci_dip, "dev=%x: flags=%x\n", dev, flags); in pci_close()
247 DEBUG2(DBG_IOCTL, dip, "dev=%x: cmd=%x\n", dev, cmd); in pci_ioctl()
H A Dpci_intr.c547 DEBUG2(DBG_A_INTX, dip, "pci_add_intr: pil=0x%x mondo=0x%x\n", in pci_add_intr()
609 DEBUG2(DBG_A_INTX, dip, "done! Interrupt 0x%x pil=%x\n", in pci_add_intr()
621 DEBUG2(DBG_A_INTX, dip, "Failed! Interrupt 0x%x pil=%x\n", in pci_add_intr()
666 DEBUG2(DBG_R_INTX, dip, "pci_rem_intr: pil=0x%x mondo=0x%x\n", in pci_remove_intr()
671 DEBUG2(DBG_R_INTX, dip, "pulse success mondo=%x reg=%p\n", in pci_remove_intr()
H A Dpci.c490 DEBUG2(DBG_MAP, dip, "rdip=%s%d:", in pci_map()
642 DEBUG2(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n", in pci_dma_allochdl()
745 DEBUG2(DBG_DMA_BINDH, dip, "cookie %x+%x\n", cookiep->dmac_address, in pci_dma_bindhdl()
824 DEBUG2(DBG_DMA_WIN, dip, "rdip=%s%d\n", in pci_dma_win()
873 DEBUG2(DBG_DMA_WIN, dip, in pci_dma_win()
1273 DEBUG2(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n", in pci_ctlops()
1393 DEBUG2(DBG_ATTACH, dip, "%s%d hotplug enabled", in pci_init_hotplug()
H A Dpci_ib.c89 DEBUG2(DBG_ATTACH, dip, "ib_create: slot_imr=%x, slot_cir=%x\n", in ib_create()
91 DEBUG2(DBG_ATTACH, dip, "ib_create: obio_imr=%x, obio_cir=%x\n", in ib_create()
93 DEBUG2(DBG_ATTACH, dip, "ib_create: upa0_imr=%x, upa1_imr=%x\n", in ib_create()
163 DEBUG2(DBG_IB, pci_p->pci_dip, in ib_intr_enable()
809 DEBUG2(DBG_R_INTX, ino_p->ino_ib_p->ib_pci_p->pci_dip, in ib_ino_rem_intr()
939 DEBUG2(DBG_IB, dip, "ib_set_intr_target: ino %x cpu_id %x\n", in ib_set_intr_target()
H A Dpci_dma.c75 DEBUG2(DBG_SC, dip, "addr=%x+%x pages: \n", dvma_addr, len); in pci_sc_pg_inv()
162 DEBUG2(DBG_SC, dip, "mp=%p, ctx=%x\n", mp, MP2CTX(mp)); in pci_dma_sync()
573 DEBUG2(DBG_DMA_MAP, dip, "vaddr=%p pplist=%p\n", vaddr, pplist); in pci_dma_type()
660 DEBUG2(DBG_DMA_MAP, dip, "shadow pplist=%p, %x pages, pfns=", in pci_dma_pgpfn()
772 DEBUG2(DBG_DMA_MAP, pci_p->pci_dip, "pci_dma_pfn: mp=%p pfn0=%x\n", in pci_dma_pfn()
1023 DEBUG2(DBG_DMA_MAP, dip, "fallback dvma_pages: dvma_pg=%x index=%x\n", in pci_dvma_map()
1206 DEBUG2(DBG_BYPASS, mp->dmai_rdip, "cookie %p (%x pages)\n", in pci_dma_newwin()
1459 DEBUG2(DBG_DMA_CTL, dip, in pci_dma_ctl()
H A Dpci_fdvma.c90 DEBUG2(DBG_FAST_DVMA | DBG_CONT, dip, "cookie: %x+%x\n", in pci_fdvma_load()
194 DEBUG2(DBG_DMA_CTL, dip, "DDI_DMA_RESERVE: rdip=%s%d\n", in pci_fdvma_reserve()
H A Dpcipsy.c840 DEBUG2(DBG_ATTACH, dip, "cb_create: ver=%d, mask=%x\n", l, mask); in pbm_configure()
1103 DEBUG2(DBG_ATTACH, iommu_p->iommu_pci_p->pci_dip, in pci_iommu_config()
1106 DEBUG2(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, in pci_iommu_config()
1109 DEBUG2(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, in pci_iommu_config()
2019 DEBUG2(DBG_ATTACH, rdip, "pci_thermal_rem_intr unregistered " in pci_thermal_rem_intr()
H A Dsimba.c75 #define DEBUG2(f, s, a, b) if ((f)& simba_debug_flags) \ macro
94 #define DEBUG2(f, s, a, b) macro
435 DEBUG2(D_ATTACH, "simba_attach(): clsz=%x, lt=%x\n", in simba_attach()
H A Dpci_cb.c121 DEBUG2(DBG_CB|DBG_CONT, NULL, "\tPA=%016llx data=%016llx\n", pa, reg); in cb_enable_nintr()
H A Dpci_ecc.c91 DEBUG2(DBG_ATTACH, dip, "ecc_create: ue_afsr=%x, ue_afar=%x\n", in ecc_create()
93 DEBUG2(DBG_ATTACH, dip, "ecc_create: ce_afsr=%x, ce_afar=%x\n", in ecc_create()
H A Dpci_pci.c872 DEBUG2(DBG_PWR, ddi_get_parent(child), in ppb_initchild()
880 DEBUG2(DBG_PWR, ddi_get_parent(child), in ppb_initchild()
1021 DEBUG2(DBG_PWR, ddi_get_parent(dip), in ppb_removechild()
1307 DEBUG2(DBG_PWR, dip, "ppb_pwr: failing power request " in ppb_pwr()
/titanic_50/usr/src/cmd/rmt/
H A Drmt.c125 #define DEBUG2(f, a, b) if (debug) (void) fprintf(debug, (f), (a), (b)) macro
214 DEBUG2("rmtd: L %s %s\n", count, pos); in main()
398 DEBUG2(gettext("%s: garbage command '%c'\n"), in main()
433 DEBUG2("rmtd: O %s %s\n", device, mode); in main()
472 DEBUG2("rmtd: E %d (%s)\n", Errno, errstr); in respond()
503 DEBUG2(gettext("%s: cannot allocate %ld-byte buffer\n"), in checkbuf()
/titanic_50/usr/src/lib/libbsm/common/
H A Daudit_class.c44 #ifdef DEBUG2
259 #ifdef DEBUG2 in xcacheauclass()
278 #ifdef DEBUG2 in xcacheauclass()
H A Daudit_event.c70 #ifdef DEBUG2
330 #ifdef DEBUG2 in cacheauevent()
354 #ifdef DEBUG2 in cacheauevent()
/titanic_50/usr/src/uts/common/io/hotplug/hpcsvc/
H A Dhpcsvc.c53 #define DEBUG2(fmt, a1, a2) \ macro
60 #define DEBUG2(fmt, a1, a2) macro
326 DEBUG2("hpc_nexus_register_bus: %s%d", in hpc_nexus_register_bus()
392 DEBUG2("hpc_nexus_unregister_bus: %s%d", in hpc_nexus_unregister_bus()
574 DEBUG2("hpc_slot_unregister: handlep=%x, slotp=%x", handlep, slotp); in hpc_slot_unregister()
718 DEBUG2("hpc_slot_event_notify: handle=%x event=%x", handle, event); in hpc_slot_event_notify()
758 DEBUG2("hpc_slot_event_notify: busp=%x event=%x", busp, event); in hpc_slot_event_notify()
/titanic_50/usr/src/uts/sun4u/sys/pci/
H A Dpci_debug.h97 #define DEBUG2(flag, dip, fmt, a1, a2) \ macro
116 #define DEBUG2(flag, dip, fmt, a1, a2) macro
/titanic_50/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c196 #define DEBUG2(fmt, a1, a2)\ macro
210 #define DEBUG2(fmt, a1, a2) macro
603 DEBUG2("configure failed: bus [0x%x] device " in pcicfg_configure()
736 DEBUG2("Cleaning up device [0x%x] function [0x%x]\n", in pcicfg_configure()
948 DEBUG2("Need to free bus [%d] range [%d]\n", in pcicfg_configure_ntbridge()
1034 DEBUG2("Connector requested [0x%llx], needs [0x%llx] bytes of memory\n", in pcicfg_ntbridge_allocate_resources()
1062 DEBUG2("Connector requested [0x%llx], needs [0x%llx] bytes of IO\n", in pcicfg_ntbridge_allocate_resources()
1091 DEBUG2("Connector requested [0x%llx], needs [0x%llx] bytes of PF " in pcicfg_ntbridge_allocate_resources()
1094 DEBUG2("MEMORY BASE = [0x%lx] length [0x%lx]\n", in pcicfg_ntbridge_allocate_resources()
1096 DEBUG2("IO BASE = [0x%x] length [0x%x]\n", in pcicfg_ntbridge_allocate_resources()
[all …]
/titanic_50/usr/src/uts/sun4/io/
H A Dpcicfg.c237 #define DEBUG2(fmt, a1, a2)\ macro
248 #define DEBUG2(fmt, a1, a2) macro
637 DEBUG2("device_type property missing for %s#%d", in pcicfg_pcie_dev()
764 DEBUG2("configure failed: " in pcicfg_configure()
875 DEBUG2("Cleaning up device [0x%x] function [0x%x]\n", in pcicfg_configure()
1080 DEBUG2("Need to free bus [%d] range [%d]\n", in pcicfg_configure_ntbridge()
1170 DEBUG2("Connector requested [0x%llx], needs [0x%llx] bytes of memory\n", in pcicfg_ntbridge_allocate_resources()
1209 DEBUG2("Connector requested [0x%llx], needs [0x%llx] bytes of IO\n", in pcicfg_ntbridge_allocate_resources()
1212 DEBUG2("MEMORY BASE = [0x%x] length [0x%x]\n", in pcicfg_ntbridge_allocate_resources()
1214 DEBUG2("IO BASE = [0x%x] length [0x%x]\n", in pcicfg_ntbridge_allocate_resources()
[all …]
/titanic_50/usr/src/uts/sun4u/montecarlo/io/
H A Dhsc.c196 DEBUG2("hsc_connect: slot %d, healthy %d", hsp->hs_slot_number, in hsc_connect()
741 DEBUG2("hsc_control: slot %d, op=%x\n", hsp->hs_slot_number, request); in hsc_control()
861 DEBUG2("hsc_alloc_slot: slot %d %s", slot_number, in hsc_alloc_slot()
936 DEBUG2("hsc_slot_register: slot number %d, device number %d", in hsc_slot_register()
1264 DEBUG2("hsc_board_healthy: slot %d = %d\n", slot_number, healthy); in scsb_hsc_board_healthy()
1283 DEBUG2("healthy %s on disconnected slot %d\n", in scsb_hsc_board_healthy()
1727 DEBUG2("Registering on nexus [%s] cPCI device [%d]\n", in scsb_hsc_attach()
1794 DEBUG2("%s#%d: hsc_detach: Soft state NULL", in scsb_hsc_detach()
1865 DEBUG2("%s#%d: Soft state NULL", in scsb_hsc_freeze()
1918 DEBUG2("%s#%d: Soft state NULL", in scsb_hsc_restore()
[all …]
/titanic_50/usr/src/lib/krb5/plugins/kdb/db2/libdb2/hash/
H A Dhash_page.c1082 #ifdef DEBUG2
1161 #ifdef DEBUG2
1188 #ifdef DEBUG2
1203 #ifdef DEBUG2
1222 #ifdef DEBUG2
1310 #ifdef DEBUG2
1333 #ifdef DEBUG2
/titanic_50/usr/src/uts/sun4u/montecarlo/sys/
H A Dscsb.h688 #define DEBUG2(fmt, a1, a2)\ macro
699 #define DEBUG2(fmt, a1, a2) macro

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