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Searched refs:DCU_DC (Results 1 – 7 of 7) sorted by relevance

/titanic_50/usr/src/uts/sun4u/sys/
H A Dcheetahregs.h80 #define DCU_DC INT64_C(0x0000000000000002) /* dcache enable */ macro
99 #define DCU_CACHE (DCU_IC|DCU_DC|DCU_WE|DCU_SPE|DCU_HPE|DCU_PE)
1171 #define CH_ERR_TSTATE_DC_ON (DCU_DC << CH_ERR_DCU_TO_TSTATE_SHFT)
H A Dcheetahasm.h1194 andn %g1, DCU_DC + DCU_IC, %g2; \
1198 and %g1, DCU_DC + DCU_IC, %g1; \
/titanic_50/usr/src/uts/sun4u/cpu/
H A Dus3_cheetah_asm.s183 or %g3, DCU_DC, %g3
H A Dus3_common_asm.s60 btst DCU_DC, tmp1 /* is dcache enabled? */ ;\
145 btst DCU_DC, tmp1; /* is dcache enabled? */ \
1296 andn %g1, DCU_DC + DCU_IC, %g4
1839 andn %g1, DCU_IC + DCU_DC, %g4
H A Dus3_cheetahplus_asm.s255 or %g3, DCU_DC, %g3
H A Dus3_jalapeno_asm.s642 or %g3, DCU_DC, %g3
H A Dus3_common.c2167 DCU_DC) { in cpu_parity_error()
2251 if (cache_boot_state & DCU_DC) { in cpu_parity_error()