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Searched refs:DCSR_CYC_PEND (Results 1 – 4 of 4) sorted by relevance

/titanic_50/usr/src/uts/common/sys/
H A Decppreg.h223 #define DCSR_CYC_PEND 0x00000400 /* 1 = DMA pending */ macro
/titanic_50/usr/src/uts/sun/sys/
H A Dfdreg.h295 #define DCSR_CYC_PEND 0x00000400 /* 1 = DMA pending */ macro
/titanic_50/usr/src/uts/common/io/
H A Decpp.c5737 while (GET_DMAC_CSR(pp) & DCSR_CYC_PEND) { in cheerio_reset_dcsr()
/titanic_50/usr/src/uts/sun/io/
H A Dfd.c6391 while (get_dma_control_register(fdc) & DCSR_CYC_PEND) in reset_dma_controller()