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Searched refs:DBG_ERR_INTR (Results 1 – 8 of 8) sorted by relevance

/titanic_50/usr/src/uts/sun4/io/px/
H A Dpx_debug.h55 /* 15 */ DBG_ERR_INTR, enumerator
H A Dpx_fm.c275 DBG(DBG_ERR_INTR, dip, "Addr: 0x%llx high: 0x%llx low: 0x%llx\n", in px_in_addr_range()
651 DBG(DBG_ERR_INTR, dip, in px_pcie_log()
812 DBG(DBG_ERR_INTR, dip, "Check CFG Hdl: dip 0x%p addr 0x%x bdf=0x%x\n", in px_err_cfg_hdl_check()
865 DBG(DBG_ERR_INTR, dip, "Check PIO Hdl: dip 0x%x addr 0x%x bdf=0x%x\n", in px_err_pio_hdl_check()
917 DBG(DBG_ERR_INTR, dip, "Check PIO Hdl: dip 0x%x addr 0x%x bdf=0x%x\n", in px_err_dma_hdl_check()
/titanic_50/usr/src/uts/sun4u/io/pci/
H A Dpci_debug.c53 {DBG_ERR_INTR, "pbm_error_intr"},
H A Dpcisch.c2007 DEBUG3(DBG_ERR_INTR, pci_p->pci_dip, "pcix_log_pbm: chip_type=%d " in pcix_log_pbm()
2389 DEBUG2(DBG_ERR_INTR, dip, "pci_pbm_err_handler: prierr=0x%x " in pci_pbm_err_handler()
2451 DEBUG1(DBG_ERR_INTR, dip, "pci_pbm_err_handler: " in pci_pbm_err_handler()
2844 DEBUG1(DBG_ERR_INTR, dip, "cb_ereport_post: ereport_set: %s", buf); in cb_ereport_post()
2880 DEBUG1(DBG_ERR_INTR, dip, "iommu_ereport_post: ereport_set: %s", buf); in iommu_ereport_post()
2909 DEBUG1(DBG_ERR_INTR, dip, "pcix_ereport_post: ereport_post: %s", buf); in pcix_ereport_post()
/titanic_50/usr/src/uts/sun4u/sys/pci/
H A Dpci_debug.h53 #define DBG_ERR_INTR 0x400ull macro
/titanic_50/usr/src/uts/sun4v/io/px/
H A Dpx_err.c532 DBG(DBG_ERR_INTR, dip, in px_err_log_handle()
548 DBG(DBG_ERR_INTR, dip, in px_err_log_handle()
H A Dpx_lib4v.c2090 DBG(DBG_ERR_INTR, dip, "px_panic_domain: handle 0x%lx, ino %d, " in px_panic_domain()
2096 DBG(DBG_ERR_INTR, dip, "pci_error_send failed, ret 0x%lx\n", in px_panic_domain()
2099 DBG(DBG_ERR_INTR, dip, "pci_error_send worked\n"); in px_panic_domain()
/titanic_50/usr/src/uts/sun4u/io/px/
H A Dpx_err.c1064 DBG(DBG_ERR_INTR, rpdip, in px_err_log_handle()