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Searched refs:C_AFSR_L3_EDC (Results 1 – 4 of 4) sorted by relevance

/titanic_50/usr/src/uts/sun4u/sys/
H A Dus3_module.h272 #define C_AFSR_EXT_CECC_ERRS (C_AFSR_L3_EDU | C_AFSR_L3_EDC | \
297 C_AFSR_L3_UCC | C_AFSR_L3_EDU | C_AFSR_L3_EDC | \
302 C_AFSR_L3_EDU | C_AFSR_L3_EDC | C_AFSR_L3_WDU | \
H A Dcheetahregs.h271 #define C_AFSR_L3_EDC INT64_C(0x0000000000000080) /* L3 cache CE */ macro
/titanic_50/usr/src/uts/sun4u/cpu/
H A Dus3_cheetahplus.c573 C_AFSR_L3_EDC, "L3_EDC ", ECC_C_TRAP,
672 C_AFSR_THCE | C_AFSR_L3_EDC | C_AFSR_L3_WDC | C_AFSR_L3_CPC |
720 C_AFSR_L3_EDC | C_AFSR_L3_WDC | C_AFSR_L3_CPC,
H A Dus3_common.c6472 if (afsr_errs & (C_AFSR_EDC | C_AFSR_CPC | C_AFSR_WDC | C_AFSR_L3_EDC |
6513 C_AFSR_L3_EDC | C_AFSR_L3_WDC)) {
7246 case C_AFSR_L3_EDC: