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Searched refs:CSR_XS (Results 1 – 4 of 4) sorted by relevance

/titanic_50/usr/src/uts/sun4u/io/px/
H A Dpx_hlib.c209 CSR_XS(xbc_csr_base, JBUS_PARITY_CONTROL, val); in jbc_init()
221 CSR_XS(xbc_csr_base, JBC_FATAL_RESET_ENABLE, val); in jbc_init()
228 CSR_XS(xbc_csr_base, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE, -1ull); in jbc_init()
259 CSR_XS(xbc_csr_base, UBC_ERROR_LOG_ENABLE, -1ull); in ubc_init()
266 CSR_XS(xbc_csr_base, UBC_ERROR_STATUS_CLEAR, -1ull); in ubc_init()
385 CSR_XS(csr_base, TLU_CONTROL, val); in tlu_init()
566 CSR_XS(csr_base, TLU_DEVICE_CONTROL, val); in tlu_init()
597 CSR_XS(csr_base, TLU_LINK_CONTROL, val); in tlu_init()
797 CSR_XS(csr_base, LPU_RESET, val); in lpu_init()
903 CSR_XS(csr_base, LPU_LINK_LAYER_CONFIG, val); in lpu_init()
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H A Dpx_csr.h43 #define CSR_XS(base, off, val) \ macro
H A Dpx_lib4u.c1483 CSR_XS((caddr_t)pxu_p->px_address[PX_REG_XBC], JBUS_SCRATCH_1, val); in px_set_cb()
2410 CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, in px_cpr_callb()
2413 CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, in px_cpr_callb()
2459 CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, (imu_log_enable | in px_cpr_callb()
2461 CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, (imu_intr_enable | in px_cpr_callb()
2695 CSR_XS(csr_base, TLU_DEVICE_CONTROL, dev_ctrl); in px_lib_set_root_complex_mps()
2720 CSR_XS(csr_base, LPU_TXLINK_REPLAY_TIMER_THRESHOLD, val); in px_lib_set_root_complex_mps()
2726 CSR_XS(csr_base, LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD, val); in px_lib_set_root_complex_mps()
H A Dpx_err.c741 CSR_XS(csr_base, reg_desc_p->log_addr, log_mask); in px_err_reg_enable()
752 CSR_XS(csr_base, reg_desc_p->enable_addr, 0); in px_err_reg_enable()
753 CSR_XS(csr_base, reg_desc_p->clear_addr, -1); in px_err_reg_enable()
754 CSR_XS(csr_base, reg_desc_p->enable_addr, intr_mask); in px_err_reg_enable()
774 CSR_XS(csr_base, reg_desc_p->log_addr, val); in px_err_reg_disable()
775 CSR_XS(csr_base, reg_desc_p->enable_addr, val); in px_err_reg_disable()
990 CSR_XS(csr_base, clear_addr, ss_reg); in px_err_erpt_and_clr()