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Searched refs:CSR_WRITE_4 (Results 1 – 3 of 3) sorted by relevance

/titanic_50/usr/src/uts/common/io/yge/
H A Dyge.c424 CSR_WRITE_4(dev, MR_ADDR(port->p_port, GMAC_CTRL), gmac); in yge_mii_notify()
576 CSR_WRITE_4(dev, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); in yge_phy_power()
634 CSR_WRITE_4(dev, B2_GP_IO, our); in yge_phy_power()
757 CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); in yge_reset()
758 CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); in yge_reset()
760 CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); in yge_reset()
761 CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); in yge_reset()
777 CSR_WRITE_4(dev, B2_I2C_IRQ, I2C_CLR_IRQ); in yge_reset()
816 CSR_WRITE_4(dev, B0_HWE_IMSK, 0); in yge_reset()
818 CSR_WRITE_4(dev, B0_IMSK, 0); in yge_reset()
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H A Dyge.h1816 #define CSR_WRITE_4(d, reg, v) \ macro
1830 #define CSR_PCI_WRITE_4(d, reg, v) CSR_WRITE_4(d, Y2_CFG_SPC + (reg), (v))
/titanic_50/usr/src/uts/common/io/pcn/
H A Dpcn.c60 #define CSR_WRITE_4(pcnp, reg, val) \ macro
518 CSR_WRITE_4(pcnp, PCN_IO32_RAP, PCN_CSR_EXTCTL1); in pcn_quiesce()
519 CSR_WRITE_4(pcnp, PCN_IO32_RDP, CSR_READ_4(pcnp, PCN_IO32_RDP) & in pcn_quiesce()
522 CSR_WRITE_4(pcnp, PCN_IO32_RAP, PCN_CSR_CSR); in pcn_quiesce()
523 CSR_WRITE_4(pcnp, PCN_IO32_RDP, in pcn_quiesce()
1028 CSR_WRITE_4(pcnp, PCN_IO32_RDP, 0); in pcn_initialize()
1416 CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg); in pcn_csr_read()
1438 CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg); in pcn_csr_write()
1439 CSR_WRITE_4(pcnp, PCN_IO32_RDP, val); in pcn_csr_write()
1449 CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg); in pcn_bcr_read()
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