Home
last modified time | relevance | path

Searched refs:CSR_WRITE_2 (Results 1 – 3 of 3) sorted by relevance

/titanic_50/usr/src/uts/common/io/yge/
H A Dyge.c515 CSR_WRITE_2(port->p_dev, in yge_init_rx_ring()
610 CSR_WRITE_2(dev, B0_CTST, Y2_HW_WOL_OFF); in yge_phy_power()
644 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL), in yge_phy_power()
646 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL), in yge_phy_power()
697 CSR_WRITE_2(dev, B28_Y2_ASF_STAT_CMD, status); in yge_reset()
701 CSR_WRITE_2(dev, B0_CTST, Y2_ASF_DISABLE); in yge_reset()
764 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL), in yge_reset()
768 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); in yge_reset()
774 CSR_WRITE_2(dev, B0_CTST, Y2_LED_STAT_ON); in yge_reset()
871 CSR_WRITE_2(dev, STAT_LAST_IDX, YGE_STAT_RING_CNT - 1); in yge_reset()
[all …]
H A Dyge.h1818 #define CSR_WRITE_2(d, reg, v) \ macro
1831 #define CSR_PCI_WRITE_2(d, reg, v) CSR_WRITE_2(d, Y2_CFG_SPC + (reg), (v))
1841 CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val))
/titanic_50/usr/src/uts/common/io/pcn/
H A Dpcn.c63 #define CSR_WRITE_2(pcnp, reg, val) \ macro
1428 CSR_WRITE_2(pcnp, PCN_IO16_RAP, reg); in pcn_csr_read16()
1461 CSR_WRITE_2(pcnp, PCN_IO16_RAP, reg); in pcn_bcr_read16()