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Searched refs:CPU (Results 1 – 25 of 352) sorted by relevance

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/titanic_50/usr/src/uts/i86pc/os/
H A Dmlsetup.c204 cpuid_getvendor(CPU) == X86_VENDOR_Intel && in mlsetup()
205 cpuid_getfamily(CPU) == 6 && in mlsetup()
206 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) && in mlsetup()
233 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && in mlsetup()
234 cpuid_getfamily(CPU) <= 0xf && in mlsetup()
237 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && in mlsetup()
238 cpuid_getfamily(CPU) <= 6 && in mlsetup()
255 patch_memops(cpuid_getvendor(CPU)); in mlsetup()
305 THREAD_ONPROC(&t0, CPU); in mlsetup()
325 CPU->cpu_thread = &t0; in mlsetup()
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H A Dx_call.c314 struct machcpu *mcpup = &(CPU->cpu_m); in xc_serv()
337 if (BT_TEST(xc_priority_set, CPU->cpu_id)) { in xc_serv()
342 XC_BT_CLEAR(xc_priority_set, CPU->cpu_id); in xc_serv()
470 if (BT_TEST(set, CPU->cpu_id) && (CPU->cpu_flags & CPU_READY) && in xc_common()
481 data = &CPU->cpu_m.xc_data; in xc_common()
490 CPU->cpu_m.xc_wait_cnt = 0; in xc_common()
501 msg = xc_extract(&CPU->cpu_m.xc_free); in xc_common()
505 if (msg->xc_master != CPU->cpu_id) in xc_common()
514 (void) xc_increment(&CPU->cpu_m); in xc_common()
516 ++CPU->cpu_m.xc_wait_cnt; in xc_common()
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H A Dmp_startup.c158 (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN); in init_cpu_info()
159 (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN); in init_cpu_info()
406 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); in mp_cpu_configure_common()
424 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); in mp_cpu_configure_common()
427 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); in mp_cpu_configure_common()
429 cp->cpu_idt = CPU->cpu_idt; in mp_cpu_configure_common()
564 if (cp->cpu_idt != CPU->cpu_idt) in mp_cpu_unconfigure_common()
728 family = cpuid_getfamily(CPU); in opteron_get_nnodes()
802 ASSERT(cpu == CPU); in workaround_errata()
1505 init_cpu_info(CPU); in start_other_cpus()
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H A Dmp_machdep.c425 (*CPU->cpu_m.mcpu_idle_cpu)(); in cpu_idle_adaptive()
454 cpu_t *cpup = CPU; in cpu_idle()
591 if (cpu != CPU) in cpu_wakeup()
621 if (cpu_found != CPU->cpu_seqid) { in cpu_wakeup()
663 volatile uint32_t *mcpu_mwait = CPU->cpu_m.mcpu_mwait; in cpu_idle_mwait()
664 cpu_t *cpup = CPU; in cpu_idle_mwait()
844 CPU->cpu_intr_actv |= (1 << (XC_SYS_PIL - 1)); in mp_disable_intr()
860 CPU->cpu_intr_actv &= ~(1 << (XC_SYS_PIL - 1)); in mp_enable_intr()
1032 CPU->cpu_m.mcpu_idle_cpu = cpu_idle; in mach_init()
1036 CPU->cpu_m.mcpu_mwait = cpuid_mwait_alloc(CPU); in mach_init()
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/titanic_50/usr/src/uts/sun4/os/
H A Dmlsetup.c167 THREAD_ONPROC(&t0, CPU); in mlsetup()
194 CPU->cpu_thread = &t0; in mlsetup()
195 CPU->cpu_dispthread = &t0; in mlsetup()
197 CPU->cpu_disp = &cpu0_disp; in mlsetup()
198 CPU->cpu_disp->disp_cpu = CPU; in mlsetup()
199 CPU->cpu_idle_thread = &t0; in mlsetup()
200 CPU->cpu_flags = CPU_RUNNING; in mlsetup()
201 CPU->cpu_id = getprocessorid(); in mlsetup()
202 CPU->cpu_dispatch_pri = t0.t_pri; in mlsetup()
208 init_cpu_mstate(CPU, CMS_SYSTEM); in mlsetup()
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H A Dmp_states.c67 CPU->cpu_m.in_prom = 1; in cpu_idle_self()
73 kern_idle[CPU->cpu_id] = 1; in cpu_idle_self()
74 while (kern_idle[CPU->cpu_id]) in cpu_idle_self()
77 CPU->cpu_m.in_prom = 0; in cpu_idle_self()
95 cpuid = CPU->cpu_id; in idle_other_cpus()
137 int cpuid = CPU->cpu_id; in resume_other_cpus()
221 ASSERT(CPU->cpu_id != cpuid); in mp_cpu_quiesce()
H A Dintr.c164 CPU->cpu_m.poke_cpu_outstanding = B_FALSE; in poke_cpu_intr()
222 if (siron_cpu_inum && siron_cpu_inum[CPU->cpu_id] != 0) in siron()
223 inum = siron_cpu_inum[CPU->cpu_id]; in siron()
285 int cpuid = CPU->cpu_id; in siron_poke_cpu()
356 mcpu = &CPU->cpu_m; in intr_dequeue_req()
357 cpu_id = CPU->cpu_id; in intr_dequeue_req()
687 cpuid = CPU->cpu_id; in intr_dist_cpuid()
702 curr_cpu = CPU; in intr_dist_cpuid()
855 if (cpuid == CPU->cpu_id) in invoke_softint()
/titanic_50/usr/src/cmd/fm/dicts/
H A DAMD.po99 msgstr "The number of errors associated with this CPU has exceeded acceptable levels. Refer to %s …
101 msgstr "An attempt will be made to remove this CPU from service."
105 msgstr "Schedule a repair procedure to replace the affected CPU. Use 'fmadm faulty' to identify th…
115 msgstr "The number of errors associated with this CPU has exceeded acceptable levels. Refer to %s …
117 msgstr "An attempt will be made to remove this CPU from service."
121 msgstr "Schedule a repair procedure to replace the affected CPU. Use 'fmadm faulty' to identify th…
131 msgstr "The number of errors associated with this CPU has exceeded acceptable levels. Refer to %s …
133 msgstr "An attempt will be made to remove this CPU from service."
137 msgstr "Schedule a repair procedure to replace the affected CPU. Use 'fmadm faulty' to identify th…
147 msgstr "The number of errors associated with this CPU has exceeded acceptable levels. Refer to %s …
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/titanic_50/usr/src/uts/common/disp/
H A Ddisp_lock.c79 if (CPU_ON_INTR(CPU) != 0) in disp_lock_exit_high()
94 if (CPU_ON_INTR(CPU) != 0) in disp_lock_exit()
97 if (CPU->cpu_kprunrun) { in disp_lock_exit()
108 if (CPU_ON_INTR(CPU) != 0) in disp_lock_exit_nopreempt()
122 if (CPU_ON_INTR(CPU) != 0) in thread_lock()
165 if (CPU_ON_INTR(CPU) != 0) in thread_lock_high()
H A Ddisp.c222 CPU->cpu_disp->disp_maxrunpri = -1; in dispinit()
223 CPU->cpu_disp->disp_max_unbound_pri = -1; in dispinit()
526 cpu_t *cp = CPU; in disp_anywork()
575 cpu_t *cp = CPU; in idle_enter()
588 cpu_t *cp = CPU; in idle_exit()
600 struct cpu *cp = CPU; /* pointer to this CPU */ in idle()
688 if (t->t_state != TS_ONPROC || t->t_disp_queue != CPU->cpu_disp) { in preempt()
694 CPU->cpu_kprunrun = 0; in preempt()
700 CPU_STATS_ADDQ(CPU, sys, inv_swtch, 1); in preempt()
731 cpup = CPU; in disp()
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/titanic_50/usr/src/uts/common/os/
H A Dcpu_event.c510 ASSERT(!CPU_ON_INTR(CPU)); in cpu_idle_register_callback()
511 ASSERT(CPU->cpu_seqid < max_ncpus); in cpu_idle_register_callback()
512 sp = &cpu_idle_cb_state[CPU->cpu_seqid]; in cpu_idle_register_callback()
568 ASSERT(!CPU_ON_INTR(CPU)); in cpu_idle_unregister_callback()
569 ASSERT(CPU->cpu_seqid < max_ncpus); in cpu_idle_unregister_callback()
570 sp = &cpu_idle_cb_state[CPU->cpu_seqid]; in cpu_idle_unregister_callback()
642 ctx = CPU_IDLE_GET_CTX(CPU); in cpu_idle_enter()
643 ASSERT(CPU->cpu_seqid < max_ncpus); in cpu_idle_enter()
644 sp = &cpu_idle_cb_state[CPU->cpu_seqid]; in cpu_idle_enter()
649 if (CPU_IN_SET(cpu_idle_intercept_set, CPU->cpu_id)) { in cpu_idle_enter()
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H A Dclock_tick.c314 if (CPU == cp) { in clock_tick_process()
346 ((cp != CPU) || (t != cp->cpu_thread->t_intr))) { in clock_tick_process()
432 if (clock_cpu_id != CPU->cpu_id) in clock_tick_schedule()
433 clock_cpu_id = CPU->cpu_id; in clock_tick_schedule()
479 clock_tick_process(CPU, LBOLT_NO_ACCOUNT, clock_tick_pending); in clock_tick_schedule()
496 if (cp == CPU) in clock_tick_schedule()
543 clock_tick_process(CPU, mylbolt, pending); in clock_tick_execute_common()
551 if ((cp == NULL) || (cp == CPU) || (cp->cpu_id == clock_cpu_id)) in clock_tick_execute_common()
558 if ((cp == NULL) || (cp == CPU) || (cp->cpu_id == clock_cpu_id)) in clock_tick_execute_common()
578 if (!CLOCK_TICK_XCALL_SAFE(CPU)) in clock_tick_execute()
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H A Dpg.c242 pg_cmt_cpu_startup(CPU); in pg_init()
256 pghw_physid_create(CPU); in pg_cpu0_init()
263 (void) pg_cpu_init(CPU, B_FALSE); in pg_cpu0_init()
264 pg_cpupart_in(CPU, &cp_default); in pg_cpu0_init()
265 pg_cpu_active(CPU); in pg_cpu0_init()
281 pg_cpu_inactive(CPU); in pg_cpu0_reinit()
282 pg_cpupart_out(CPU, &cp_default); in pg_cpu0_reinit()
283 pg_cpu_fini(CPU, NULL); in pg_cpu0_reinit()
285 (void) pg_cpu_init(CPU, B_FALSE); in pg_cpu0_reinit()
286 pg_cpupart_in(CPU, &cp_default); in pg_cpu0_reinit()
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/titanic_50/usr/src/uts/sun4/ml/
H A Dproc_init.s80 ! Initialize CPU state registers
130 ! we don't have the cache on yet for this CPU.
133 sll %l1, CPTRSHIFT, %l2 ! offset into CPU vector.
134 ldn [%l3 + %l2], %l3 ! pointer to CPU struct
149 ! Resume the thread allocated for the CPU.
/titanic_50/usr/src/cmd/picl/plugins/sun4u/schumacher/frutree/
H A Dsystem-board.info33 NODE CPU location
34 PROP Label string r 0 "CPU 0"
39 NODE CPU location
40 PROP Label string r 0 "CPU 1"
72 * create the fru modules for CPU
74 name:/frutree/chassis/MB/SUNW,Netra-CP3010/CPU?GeoAddr=1
77 name:/frutree/chassis/MB/SUNW,Netra-CP3010/CPU?GeoAddr=2
81 * _fru_parent CPU devices
84 REFPROP _fru_parent /frutree/chassis/MB/SUNW,Netra-CP3010/CPU?GeoAddr=1/cpu-module
87 REFPROP _fru_parent /frutree/chassis/MB/SUNW,Netra-CP3010/CPU?GeoAddr=2/cpu-module
/titanic_50/usr/src/uts/common/sys/
H A Dftrace.h103 if (CPU->cpu_ftrace.ftd_state & FTRACE_ENABLED) \
108 if (CPU->cpu_ftrace.ftd_state & FTRACE_ENABLED) \
113 if (CPU->cpu_ftrace.ftd_state & FTRACE_ENABLED) \
118 if (CPU->cpu_ftrace.ftd_state & FTRACE_ENABLED) \
/titanic_50/usr/src/uts/intel/dtrace/
H A Ddtrace_isa.c51 uintptr_t caller = CPU->cpu_dtrace_caller; in dtrace_getpcstack()
53 if ((on_intr = CPU_ON_INTR(CPU)) != 0) in dtrace_getpcstack()
54 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME)); in dtrace_getpcstack()
122 (volatile uint16_t *)&cpu_core[CPU->cpu_id].cpuc_dtrace_flags; in dtrace_getustack_common()
144 cpu_core[CPU->cpu_id].cpuc_dtrace_illval = sp; in dtrace_getustack_common()
194 cpu_core[CPU->cpu_id].cpuc_dtrace_illval = sp; in dtrace_getustack_common()
308 (volatile uint16_t *)&cpu_core[CPU->cpu_id].cpuc_dtrace_flags; in dtrace_getufpstack()
513 if ((on_intr = CPU_ON_INTR(CPU)) != 0) in dtrace_getstackdepth()
514 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME)); in dtrace_getstackdepth()
661 cpu_core[CPU->cpu_id].cpuc_dtrace_illval = uaddr; in dtrace_copycheck()
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/titanic_50/usr/src/uts/common/inet/
H A Dtcp_stats.h209 BUMP_MIB(&(tcps)->tcps_sc[CPU->cpu_seqid]->tcp_sc_mib, x)
212 UPDATE_MIB(&(tcps)->tcps_sc[CPU->cpu_seqid]->tcp_sc_mib, x, y)
217 &((tcps)->tcps_sc[CPU->cpu_seqid]->tcp_sc_stats.x))
228 ((tcps)->tcps_sc[CPU->cpu_seqid]->tcp_sc_stats.x++)
230 ((tcps)->tcps_sc[CPU->cpu_seqid]->tcp_sc_stats.x += (n))
232 ((tcps)->tcps_sc[CPU->cpu_seqid]->tcp_sc_stats.x = (n))
/titanic_50/usr/src/uts/sun4u/os/
H A Dmach_startup.c110 intr_init(CPU); /* init interrupt request free list */ in setup_trap_table()
228 cpu_t *cpup = CPU; in cpu_halt()
241 if (CPU->cpu_flags & CPU_OFFLINE) in cpu_halt()
316 (!hset_update && (CPU->cpu_flags & CPU_OFFLINE)))) { in cpu_halt()
368 if (cpu != CPU) in cpu_wakeup()
401 if (cpu_found != CPU->cpu_seqid) in cpu_wakeup()
H A Dmach_mp_states.c38 cpu_idle_ecache_scrub(CPU); in set_idle_cpu()
48 cpu_busy_ecache_scrub(CPU); in unset_idle_cpu()
/titanic_50/usr/src/uts/sun4v/os/
H A Dmach_startup.c87 mmu_fault_status_area + (MMFSA_SIZE * CPU->cpu_id); in setup_trap_table()
89 intr_init(CPU); /* init interrupt request free list */ in setup_trap_table()
108 cpu_t *cpup = CPU; in cpu_halt()
121 if (CPU->cpu_flags & CPU_OFFLINE) in cpu_halt()
196 (!hset_update && (CPU->cpu_flags & CPU_OFFLINE)))) { in cpu_halt()
246 if (cpu != CPU) in cpu_wakeup()
276 if (cpu_found != CPU->cpu_seqid) in cpu_wakeup()
/titanic_50/usr/src/pkg/manifests/
H A Dsystem-kernel-cpu-counters.mf33 set name=pkg.description value="Kernel support for CPU Performance Counters"
34 set name=pkg.summary value="CPU Performance Counter driver"
70 desc="Kernel support for CPU Performance Counters" \
71 name="CPU Performance Counter driver"
73 desc="Kernel support for CPU Performance Counters" \
74 name="CPU Performance Counter driver"
76 desc="Kernel support for CPU Performance Counters" \
77 name="CPU Performance Counter driver"
/titanic_50/usr/src/uts/sun4u/cpu/
H A Dus3_common.c919 CHEETAH_LIVELOCK_ENTRY_SET(histp, buddy, CPU->cpu_id); in mondo_recover()
1047 if ((CPU->cpu_next_onln != CPU) && (sendmondo_in_recover == 0)) { in cheetah_nudge_buddy()
1048 xt_one(CPU->cpu_next_onln->cpu_id, (xcfunc_t *)xt_sync_tl1, in cheetah_nudge_buddy()
1081 CPU_STATS_ADDQ(CPU, sys, xcalls, 1); in send_one_mondo()
1259 myid = CPU->cpu_id; in cpu_check_other_cpus_logout()
1319 if (CPU_PRIVATE(CPU) == NULL) { in cpu_fast_ecc_error()
1324 clop = CPU_PRIVATE_PTR(CPU, chpr_fecctl0_logout); in cpu_fast_ecc_error()
1389 aflt->flt_inst = CPU->cpu_id; in cpu_log_fast_ecc_error()
1423 if (IS_PANTHER(cpunodes[CPU->cpu_id].implementation)) { in cpu_log_fast_ecc_error()
1511 if (ch_err_tl1_paddrs[CPU->cpu_id] == 0) { in cpu_tl1_error()
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/titanic_50/usr/src/uts/sun4u/starfire/io/
H A Didn_xf.c191 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); in cic_read_domain_mask()
210 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); in cic_read_sm_mask()
229 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); in cic_write_sm_mask()
236 if (pc_prep_cic_buffer(CPU->cpu_id, (uint_t)sm_mask) < 0) in cic_write_sm_mask()
268 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); in cic_read_sm_bar()
296 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); in cic_write_sm_bar()
305 if (pc_prep_cic_buffer(CPU->cpu_id, sm_bar_msb) < 0) in cic_write_sm_bar()
332 if (pc_prep_cic_buffer(CPU->cpu_id, sm_bar_lsb) < 0) in cic_write_sm_bar()
364 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); in cic_read_sm_lar()
392 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); in cic_write_sm_lar()
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/titanic_50/usr/src/uts/intel/ia32/os/
H A Dcpc_subr.c193 return (kcpc_pcbe_tryload(cpuid_getvendorstr(CPU), cpuid_getfamily(CPU), in kcpc_hw_load_pcbe()
194 cpuid_getmodel(CPU), cpuid_getstep(CPU))); in kcpc_hw_load_pcbe()

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