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Searched refs:CMI_ERRDISP_INCONSISTENT (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/i86pc/sys/
H A Dcpu_module_impl.h90 #define CMI_ERRDISP_INCONSISTENT 0x00100000ULL macro
/titanic_50/usr/src/uts/i86pc/cpu/generic_cpu/
H A Dgcpu_mca.c680 { CMI_ERRDISP_INCONSISTENT, in gcpu_ereport_add_logout()
953 !(gbl->gbl_disp & CMI_ERRDISP_INCONSISTENT)) { in gcpu_mca_drain()
976 (gbl->gbl_disp & CMI_ERRDISP_INCONSISTENT)) { in gcpu_mca_drain()
1401 if (gbl->gbl_disp & CMI_ERRDISP_INCONSISTENT) in gcpu_mca_process()
1822 CMI_ERRDISP_INCONSISTENT; in gcpu_mca_logout()
1826 gbl->gbl_disp |= CMI_ERRDISP_INCONSISTENT; in gcpu_mca_logout()