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Searched refs:CH_ERR_TL1_SDW_AFSR (Results 1 – 4 of 4) sorted by relevance

/titanic_50/usr/src/uts/sun4u/cpu/
H A Dus3_cheetah_asm.s246 ldxa [%g1 + CH_ERR_TL1_SDW_AFSR]%asi, %g4
H A Dus3_cheetahplus_asm.s325 ldxa [%g1 + CH_ERR_TL1_SDW_AFSR]%asi, %g4
366 ldxa [%g1 + CH_ERR_TL1_SDW_AFSR]%asi, %g3
H A Dus3_jalapeno_asm.s705 ldxa [%g1 + CH_ERR_TL1_SDW_AFSR]%asi, %g4
/titanic_50/usr/src/uts/sun4u/sys/
H A Dcheetahregs.h1182 #define CH_ERR_TL1_SDW_AFSR (CH_ERR_TL1_SDW_DATA + CH_CHD_AFSR) macro