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Searched refs:CH_ERR_TL1_FECC_ENTER (Results 1 – 4 of 4) sorted by relevance

/titanic_50/usr/src/uts/sun4u/cpu/
H A Dus3_cheetah_asm.s110 CH_ERR_TL1_FECC_ENTER;
H A Dus3_cheetahplus_asm.s181 CH_ERR_TL1_FECC_ENTER;
H A Dus3_jalapeno_asm.s563 CH_ERR_TL1_FECC_ENTER;
/titanic_50/usr/src/uts/sun4u/sys/
H A Dcheetahasm.h1192 #define CH_ERR_TL1_FECC_ENTER \ macro