Searched refs:CHIP_REV_IS_SLOW (Results 1 – 6 of 6) sorted by relevance
3800 u8 offset = (CHIP_REV_IS_SLOW(pdev) ? in ecore_mcast_set_rdata_hdr_e1()4213 if (CHIP_REV_IS_SLOW(pdev)) in ecore_init_mcast_obj()4495 if (!CHIP_REV_IS_SLOW(pdev)) in ecore_init_mac_credit_pool()4507 if (!CHIP_REV_IS_SLOW(pdev)) in ecore_init_mac_credit_pool()4524 if (!CHIP_REV_IS_SLOW(pdev)) in ecore_init_mac_credit_pool()4537 if (!CHIP_REV_IS_SLOW(pdev)) in ecore_init_mac_credit_pool()
61 if (CHIP_REV_IS_SLOW(pdev)) { in lm_mcp_wait_one()
1747 if (CHIP_REV_IS_SLOW(pdev)) in lm_link_on_timer()
2720 if (CHIP_REV_IS_SLOW(pdev)) in init_link_params()3296 if((CHIP_REV_IS_SLOW(pdev) in lm_init_params()
1696 #define CHIP_REV_IS_SLOW(_p) (CHIP_REV(_p) > CHIP_REV_ASIC_MAX) macro1697 …#define CHIP_REV_IS_FPGA(_p) (CHIP_REV_IS_SLOW(_p) && (CHIP_REV(_p) & CHIP_REV_SIM_IS_FPGA))1698 …#define CHIP_REV_IS_EMUL(_p) (CHIP_REV_IS_SLOW(_p) && !(CHIP_REV(_p)& CHIP_REV_SIM_IS_FPGA)…1699 #define CHIP_REV_IS_ASIC(_p) (!CHIP_REV_IS_SLOW(_p))
93 #define CHIP_REV_IS_SLOW(_chip_id) \ macro96 (CHIP_REV_IS_SLOW(_chip_id)&& \99 (CHIP_REV_IS_SLOW(_chip_id)&& \2064 if (CHIP_REV_IS_SLOW(params->chip_id)) { in elink_emac_enable()14022 !CHIP_REV_IS_SLOW(params->chip_id)) { in elink_phy_init()14148 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(params->chip_id))) { in elink_link_reset()14171 if (!CHIP_REV_IS_SLOW(params->chip_id)) in elink_link_reset()