Searched refs:CHANNELS_PER_MEMORY_CONTROLLER (Results 1 – 5 of 5) sorted by relevance
76 CHANNELS_PER_MEMORY_CONTROLLER * MAX_DIMMS_PER_CHANNEL]; in check_serial_number()139 slot = (dsp->controller * CHANNELS_PER_MEMORY_CONTROLLER * in dimm_label()142 last_slot = MAX_MEMORY_CONTROLLERS * CHANNELS_PER_MEMORY_CONTROLLER * in dimm_label()157 CHANNELS_PER_MEMORY_CONTROLLER * in dimm_label()168 CHANNELS_PER_MEMORY_CONTROLLER) { in dimm_label()173 CHANNELS_PER_MEMORY_CONTROLLER * in dimm_label()195 if (dsp->channel == CHANNELS_PER_MEMORY_CONTROLLER) { in dimm_label()286 MAX_MEMORY_CONTROLLERS * CHANNELS_PER_MEMORY_CONTROLLER * in init_dimms()293 dimmpp += CHANNELS_PER_MEMORY_CONTROLLER * in init_dimms()297 for (j = 0; j < CHANNELS_PER_MEMORY_CONTROLLER; j++) { in init_dimms()
62 extern sag_ch_t sag_ch[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]64 extern rir_t rir[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]66 extern dod_t dod_reg[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]
44 sag_ch_t sag_ch[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]46 rir_t rir[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]48 dod_t dod_reg[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]73 for (i = 0; i < CHANNELS_PER_MEMORY_CONTROLLER; i++) { in channel_in_interleave()80 for (i = 0; i < CHANNELS_PER_MEMORY_CONTROLLER; i++) { in channel_in_interleave()965 CHANNELS_PER_MEMORY_CONTROLLER) in mem_reg_init()969 for (j = 0; j < CHANNELS_PER_MEMORY_CONTROLLER; j++) { in mem_reg_init()
195 int nchannels = CHANNELS_PER_MEMORY_CONTROLLER; in inhm_dimmlist()204 dimmpp = &nhm_dimms[node * CHANNELS_PER_MEMORY_CONTROLLER * in inhm_dimmlist()
217 #define CHANNELS_PER_MEMORY_CONTROLLER 3 macro