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Searched refs:A_MC5_INT_CAUSE (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/io/chxge/com/
H A Dmc5.c550 t1_write_reg_4(mc5->adapter, A_MC5_INT_CAUSE, 0xffffffff); in t1_mc5_intr_clear()
555 t1_write_reg_4(mc5->adapter, A_MC5_INT_CAUSE, 0xffffffff); in t1_mc5_intr_clear()
565 u32 cause = t1_read_reg_4(adap, A_MC5_INT_CAUSE); in t1_mc5_intr_handler()
626 t1_write_reg_4(adap, A_MC5_INT_CAUSE, cause); in t1_mc5_intr_handler()
H A Dregs.h1996 #define A_MC5_INT_CAUSE 0xc44 macro