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Searched refs:write_reg (Results 1 – 19 of 19) sorted by relevance

/titanic_44/usr/src/uts/common/io/audio/drv/audiop16x/
H A Daudiop16x.c145 write_reg(p16x_dev_t *dev, int reg, int chn, unsigned int value) in write_reg() function
239 write_reg(dev, CRFA, 0, 0); in p16x_start()
240 write_reg(dev, CRCAV, 0, 0); in p16x_start()
246 write_reg(dev, PTBA, i, 0); in p16x_start()
247 write_reg(dev, PTBS, i, 0); in p16x_start()
248 write_reg(dev, PTCA, i, 0); in p16x_start()
249 write_reg(dev, PFEA, i, 0); in p16x_start()
250 write_reg(dev, CPFA, i, 0); in p16x_start()
251 write_reg(dev, CPCAV, i, 0); in p16x_start()
499 write_reg(dev, PTBA, i, 0); in p16x_hwinit()
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/titanic_44/usr/src/uts/common/io/e1000api/
H A De1000_82541.c106 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_82541()
713 ret_val = phy->ops.write_reg(hw, in e1000_config_dsp_after_link_change_82541()
744 ret_val = phy->ops.write_reg(hw, in e1000_config_dsp_after_link_change_82541()
768 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); in e1000_config_dsp_after_link_change_82541()
774 ret_val = phy->ops.write_reg(hw, 0x0000, in e1000_config_dsp_after_link_change_82541()
788 ret_val = phy->ops.write_reg(hw, in e1000_config_dsp_after_link_change_82541()
795 ret_val = phy->ops.write_reg(hw, 0x0000, in e1000_config_dsp_after_link_change_82541()
803 ret_val = phy->ops.write_reg(hw, 0x2F5B, in e1000_config_dsp_after_link_change_82541()
825 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); in e1000_config_dsp_after_link_change_82541()
831 ret_val = phy->ops.write_reg(hw, 0x0000, in e1000_config_dsp_after_link_change_82541()
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H A De1000_phy.c93 phy->ops.write_reg = e1000_null_write_reg; in e1000_init_phy_ops_generic()
265 if (!hw->phy.ops.write_reg) in e1000_phy_reset_dsp_generic()
268 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); in e1000_phy_reset_dsp_generic()
272 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); in e1000_phy_reset_dsp_generic()
1039 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); in e1000_set_master_slave_mode()
1073 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); in e1000_copper_link_setup_82577()
1098 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); in e1000_copper_link_setup_82577()
1170 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, in e1000_copper_link_setup_m88()
1185 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); in e1000_copper_link_setup_m88()
1214 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, in e1000_copper_link_setup_m88()
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H A De1000_82575.c207 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; in e1000_init_phy_params_82575()
214 phy->ops.write_reg = e1000_write_phy_reg_82580; in e1000_init_phy_params_82575()
219 phy->ops.write_reg = e1000_write_phy_reg_gs40g; in e1000_init_phy_params_82575()
223 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_82575()
257 ret_val = phy->ops.write_reg(hw, in e1000_init_phy_params_82575()
777 if (!(hw->phy.ops.write_reg)) in e1000_phy_hw_reset_sgmii_82575()
784 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); in e1000_phy_hw_reset_sgmii_82575()
828 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82575()
837 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_82575()
843 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82575()
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H A De1000_82540.c84 phy->ops.write_reg = e1000_write_phy_reg_m88; in e1000_init_phy_params_82540()
435 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, in e1000_setup_copper_link_82540()
513 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL, in e1000_adjust_serdes_amplitude_82540()
544 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); in e1000_set_vco_speed_82540()
553 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); in e1000_set_vco_speed_82540()
559 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); in e1000_set_vco_speed_82540()
568 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); in e1000_set_vco_speed_82540()
572 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, in e1000_set_vco_speed_82540()
605 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, in e1000_set_phy_mode_82540()
611 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, in e1000_set_phy_mode_82540()
H A De1000_80003es2lan.c122 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; in e1000_init_phy_params_80003es2lan()
681 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
696 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
744 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, in e1000_phy_force_speed_duplex_80003es2lan()
1058 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1098 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1131 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1150 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, in e1000_copper_link_setup_gg82563_80003es2lan()
1161 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, in e1000_copper_link_setup_gg82563_80003es2lan()
1175 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); in e1000_copper_link_setup_gg82563_80003es2lan()
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H A De1000_82543.c116 phy->ops.write_reg = (hw->mac.type == e1000_82543) in e1000_init_phy_params_82543()
774 if (!(hw->phy.ops.write_reg)) in e1000_polarity_reversal_workaround_82543()
781 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); in e1000_polarity_reversal_workaround_82543()
784 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); in e1000_polarity_reversal_workaround_82543()
788 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); in e1000_polarity_reversal_workaround_82543()
820 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); in e1000_polarity_reversal_workaround_82543()
824 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); in e1000_polarity_reversal_workaround_82543()
828 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); in e1000_polarity_reversal_workaround_82543()
832 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); in e1000_polarity_reversal_workaround_82543()
836 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); in e1000_polarity_reversal_workaround_82543()
H A De1000_ich8lan.c471 phy->ops.write_reg = e1000_write_phy_reg_hv; in e1000_init_phy_params_pchlan()
560 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_ich8lan()
569 phy->ops.write_reg = e1000_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
611 phy->ops.write_reg = e1000_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
1076 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg); in e1000_k1_workaround_lpt_lp()
1759 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); in e1000_check_for_copper_link_ich8lan()
2598 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); in e1000_set_mdio_slow_mode_hv()
2628 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); in e1000_hv_phy_workarounds_ich8lan()
2633 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, in e1000_hv_phy_workarounds_ich8lan()
2645 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, in e1000_hv_phy_workarounds_ich8lan()
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H A De1000_i210.c763 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr); in __e1000_access_xmdio_reg()
767 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address); in __e1000_access_xmdio_reg()
771 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA | in __e1000_access_xmdio_reg()
779 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data); in __e1000_access_xmdio_reg()
784 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0); in __e1000_access_xmdio_reg()
H A De1000_82571.c127 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_82571()
140 phy->ops.write_reg = e1000_write_phy_reg_m88; in e1000_init_phy_params_82571()
156 phy->ops.write_reg = e1000_write_phy_reg_bm2; in e1000_init_phy_params_82571()
1003 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82571()
1014 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_82571()
1020 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82571()
1035 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_82571()
1048 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_82571()
H A De1000_api.c997 if (hw->phy.ops.write_reg) in e1000_write_phy_reg()
998 return hw->phy.ops.write_reg(hw, offset, data); in e1000_write_phy_reg()
H A De1000_hw.h750 s32 (*write_reg)(struct e1000_hw *, u32, u16); member
/titanic_44/usr/src/uts/common/io/audio/drv/audiols/
H A Daudiols.c181 write_reg(audigyls_dev_t *dev, int reg, uint32_t value) in write_reg() function
239 write_reg(dev, SPC, 0x00000f00); in select_digital_enable()
241 write_reg(dev, SPC, 0x0000000f); in select_digital_enable()
253 write_reg(dev, I2C_1, tmp); in audigyls_i2c_write()
258 write_reg(dev, I2C_A, tmp); in audigyls_i2c_write()
287 write_reg(dev, SPI, orig | data); in audigyls_spi_write()
359 write_reg(dev, SA, tmp); in audigyls_start()
368 write_reg(dev, SA, tmp); in audigyls_start()
391 write_reg(dev, SA, tmp); in audigyls_stop()
397 write_reg(dev, SA, tmp); in audigyls_stop()
[all …]
/titanic_44/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_phy.c326 phy->ops.write_reg = ixgbe_write_phy_reg_generic; in ixgbe_init_phy_ops_generic()
566 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, in ixgbe_reset_phy_generic()
828 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, in ixgbe_setup_phy_link_generic()
846 hw->phy.ops.write_reg(hw, in ixgbe_setup_phy_link_generic()
864 hw->phy.ops.write_reg(hw, in ixgbe_setup_phy_link_generic()
882 hw->phy.ops.write_reg(hw, in ixgbe_setup_phy_link_generic()
899 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, in ixgbe_setup_phy_link_generic()
914 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, in ixgbe_setup_phy_link_generic()
1098 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, in ixgbe_setup_phy_link_tnx()
1113 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, in ixgbe_setup_phy_link_tnx()
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H A Dixgbe_x550.c653 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, in ixgbe_setup_eee_X550()
691 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, in ixgbe_setup_eee_X550()
1346 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, in ixgbe_enable_lasi_ext_t_x550em()
1362 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, in ixgbe_enable_lasi_ext_t_x550em()
1380 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, in ixgbe_enable_lasi_ext_t_x550em()
1397 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, in ixgbe_enable_lasi_ext_t_x550em()
1492 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; in ixgbe_init_phy_ops_X550em()
1497 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; in ixgbe_init_phy_ops_X550em()
1679 status = hw->phy.ops.write_reg(hw, in ixgbe_init_ext_t_x550em()
H A Dixgbe_api.c554 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, in ixgbe_write_phy_reg()
H A Dixgbe_type.h3754 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); member
H A Dixgbe_common.c358 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, in ixgbe_setup_fc_generic()
/titanic_44/usr/src/uts/common/io/e1000g/
H A De1000g_workarounds.c269 hw->phy.ops.write_reg(hw, IGP01E1000_PHY_DSP_RESET, dsp_value); in e1000_igp_ttl_workaround_82547()