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Searched refs:vld0 (Results 1 – 6 of 6) sorted by relevance

/titanic_44/usr/src/uts/common/io/hxge/
H A Dhpi_rxdma.c340 cfgb.bits.vld0 = 1; in hpi_rxdma_cfg_rdc_ring()
342 cfgb.bits.vld0 = 0; in hpi_rxdma_cfg_rdc_ring()
H A Dhxge_rdc_hw.h284 uint32_t vld0:1; member
290 uint32_t vld0:1;
H A Dhxge_rxdma.c2615 rcfgb_p->bits.vld0 = 1; in hxge_map_rxdma_channel_cfg_ring()
/titanic_44/usr/src/uts/common/sys/nxge/
H A Dnxge_rxdma_hw.h532 uint32_t vld0:1; member
538 uint32_t vld0:1;
/titanic_44/usr/src/uts/common/io/nxge/npi/
H A Dnpi_rxdma.c730 cfgb.bits.ldw.vld0 = 1; in npi_rxdma_cfg_rdc_ring()
732 cfgb.bits.ldw.vld0 = 0; in npi_rxdma_cfg_rdc_ring()
/titanic_44/usr/src/uts/common/io/nxge/
H A Dnxge_rxdma.c3452 rcfgb_p->bits.ldw.vld0 = 1; in nxge_map_rxdma_channel_cfg_ring()