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Searched refs:txq (Results 1 – 25 of 31) sorted by relevance

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/titanic_44/usr/src/uts/common/io/cxgbe/t4nex/
H A Dt4_sge.c108 static int alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx);
109 static int free_txq(struct port_info *pi, struct sge_txq *txq);
131 static int get_frame_txinfo(struct sge_txq *txq, mblk_t **fp,
133 static inline int fits_in_txb(struct sge_txq *txq, int len, int *waste);
134 static inline int copy_into_txb(struct sge_txq *txq, mblk_t *m, int len,
137 static inline int add_mblk(struct sge_txq *txq, struct txinfo *txinfo,
139 static void free_txinfo_resources(struct sge_txq *txq, struct txinfo *txinfo);
140 static int add_to_txpkts(struct sge_txq *txq, struct txpkts *txpkts, mblk_t *m,
142 static void write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts);
143 static int write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, mblk_t *m,
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H A Dadapter.h378 struct sge_txq *txq; /* NIC tx queues */ member
544 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) argument
545 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) argument
546 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) argument
547 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) argument
549 #define for_each_txq(pi, iter, txq) \ argument
550 txq = &pi->adapter->sge.txq[pi->first_txq]; \
551 for (iter = 0; iter < pi->ntxq; ++iter, ++txq)
608 mblk_t *t4_eth_tx(struct port_info *pi, struct sge_txq *txq, mblk_t *frame);
H A Dt4_mac.c448 struct sge_txq *txq = &sc->sge.txq[pi->first_txq]; in t4_mc_tx() local
450 return (t4_eth_tx(pi, txq, m)); in t4_mc_tx()
/titanic_44/usr/src/uts/common/io/arn/
H A Darn_xmit.c97 static void arn_tx_send_ht_normal(struct arn_softc *sc, struct ath_txq *txq,
101 static void arn_tx_txqaddbuf(struct arn_softc *sc, struct ath_txq *txq,
148 arn_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) in arn_tx_queue_tid() argument
168 list_insert_tail(&txq->axq_acq, &ac->list); in arn_tx_queue_tid()
175 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum]; in arn_tx_pause_tid() local
177 mutex_enter(&txq->axq_lock); in arn_tx_pause_tid()
181 mutex_exit(&txq->axq_lock); in arn_tx_pause_tid()
188 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum]; in arn_tx_resume_tid() local
191 mutex_enter(&txq->axq_lock); in arn_tx_resume_tid()
204 arn_tx_queue_tid(txq, tid); in arn_tx_resume_tid()
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H A Darn_main.c1730 struct ath_txq *txq; in arn_node_free() local
1740 txq = &sc->sc_txq[i]; in arn_node_free()
1741 mutex_enter(&txq->axq_lock); in arn_node_free()
1742 bf = list_head(&txq->axq_list); in arn_node_free()
1747 bf = list_next(&txq->axq_list, bf); in arn_node_free()
1749 mutex_exit(&txq->axq_lock); in arn_node_free()
2703 struct ath_txq *txq; in arn_tx_queue_update() local
2708 txq = &sc->sc_txq[arn_get_hal_qnum(ac, sc)]; in arn_tx_queue_update()
2709 (void) ath9k_hw_get_txq_props(ah, txq->axq_qnum, &qi); in arn_tx_queue_update()
2746 txq->axq_qnum, in arn_tx_queue_update()
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H A Darn_core.h525 struct ath_txq *txq; member
557 void arn_tx_cleanupq(struct arn_softc *sc, struct ath_txq *txq);
560 void arn_tx_draintxq(struct arn_softc *sc, struct ath_txq *txq);
561 void arn_txq_schedule(struct arn_softc *sc, struct ath_txq *txq);
/titanic_44/usr/src/uts/common/io/ath/
H A Dath_aux.c137 struct ath_txq *txq; in ath_set_data_queue() local
174 txq = &asc->asc_txq[qnum]; in ath_set_data_queue()
175 txq->axq_qnum = qnum; in ath_set_data_queue()
176 txq->axq_depth = 0; in ath_set_data_queue()
177 txq->axq_intrcnt = 0; in ath_set_data_queue()
178 txq->axq_link = NULL; in ath_set_data_queue()
179 list_create(&txq->axq_list, sizeof (struct ath_buf), in ath_set_data_queue()
181 mutex_init(&txq->axq_lock, NULL, MUTEX_DRIVER, NULL); in ath_set_data_queue()
209 struct ath_txq *txq = &asc->asc_txq[i]; in ath_txq_cleanup() local
211 ATH_HAL_RELEASETXQUEUE(asc->asc_ah, txq->axq_qnum); in ath_txq_cleanup()
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H A Dath_main.c679 struct ath_txq *txq; in ath_tx_start() local
788 txq = asc->asc_ac2q[WME_AC_VO]; in ath_tx_start()
800 txq = asc->asc_ac2q[WME_AC_VO]; in ath_tx_start()
811 txq = asc->asc_ac2q[WME_AC_BK]; in ath_tx_start()
878 if (++txq->axq_intrcnt >= ATH_TXINTR_PERIOD) { in ath_tx_start()
880 txq->axq_intrcnt = 0; in ath_tx_start()
905 txq->axq_qnum, rix, shortPreamble, *(uint16_t *)wh->i_dur)); in ath_tx_start()
930 mutex_enter(&txq->axq_lock); in ath_tx_start()
931 list_insert_tail(&txq->axq_list, bf); in ath_tx_start()
932 if (txq->axq_link == NULL) { in ath_tx_start()
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/titanic_44/usr/src/uts/common/io/ral/
H A Drt2560.c684 RAL_WRITE(sc, RT2560_TXCSR3, sc->txq.physaddr); in rt2560_ring_hwsetup()
1024 dr = &sc->txq.dr_desc; in rt2560_tx_intr()
1025 count = sc->txq.count; in rt2560_tx_intr()
1030 mutex_enter(&sc->txq.tx_lock); in rt2560_tx_intr()
1033 desc = &sc->txq.desc[sc->txq.next]; in rt2560_tx_intr()
1034 data = &sc->txq.data[sc->txq.next]; in rt2560_tx_intr()
1082 ral_debug(RAL_DBG_INTR, "tx done idx=%u\n", sc->txq.next); in rt2560_tx_intr()
1084 sc->txq.queued--; in rt2560_tx_intr()
1085 sc->txq.next = (sc->txq.next + 1) % RT2560_TX_RING_COUNT; in rt2560_tx_intr()
1088 sc->txq.queued < (RT2560_TX_RING_COUNT - 32)) { in rt2560_tx_intr()
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H A Drt2560_var.h162 struct rt2560_tx_ring txq; member
/titanic_44/usr/src/uts/common/io/bnxe/
H A Dbnxe_lock.c43 void BNXE_LOCK_ENTER_TX (um_device_t * pUM, int idx) { mutex_enter(&pUM->txq[idx].txMut… in BNXE_LOCK_ENTER_TX()
44 void BNXE_LOCK_EXIT_TX (um_device_t * pUM, int idx) { mutex_exit(&pUM->txq[idx].txMute… in BNXE_LOCK_EXIT_TX()
45 void BNXE_LOCK_ENTER_FREETX (um_device_t * pUM, int idx) { mutex_enter(&pUM->txq[idx].freeT… in BNXE_LOCK_ENTER_FREETX()
46 void BNXE_LOCK_EXIT_FREETX (um_device_t * pUM, int idx) { mutex_exit(&pUM->txq[idx].freeTx… in BNXE_LOCK_EXIT_FREETX()
H A Dbnxe_tx.c164 s_list_add_tail(&pUM->txq[idx].freeTxDescQ, pPktList); in BnxeTxPktsReclaim()
173 TxQueue * pTxQ = &pUM->txq[idx]; in BnxeTxSendWaitingPkt()
219 TxQueue * pTxQ = &pUM->txq[idx]; in BnxeTxRingProcess()
836 TxQueue * pTxQ = &pUM->txq[idx]; in BnxeTxSendMblk()
1055 tmpList = pUM->txq[idx].waitTxDescQ; in BnxeTxPktsAbortIdx()
1056 s_list_clear(&pUM->txq[idx].waitTxDescQ); in BnxeTxPktsAbortIdx()
1197 pTxQ = &pUM->txq[idx]; in BnxeTxPktsInitIdx()
1321 pTxQ = &pUM->txq[idx]; in BnxeTxPktsFiniIdx()
H A Dbnxe_main.c230 mutex_init(&pUM->txq[idx].txMutex, NULL, in BnxeMutexInit()
232 mutex_init(&pUM->txq[idx].freeTxDescMutex, NULL, in BnxeMutexInit()
234 pUM->txq[idx].pUM = pUM; in BnxeMutexInit()
235 pUM->txq[idx].idx = idx; in BnxeMutexInit()
304 mutex_destroy(&pUM->txq[idx].txMutex); in BnxeMutexDestroy()
305 mutex_destroy(&pUM->txq[idx].freeTxDescMutex); in BnxeMutexDestroy()
H A Dbnxe.h659 TxQueue txq[MAX_ETH_CONS]; member
933 #define BNXE_LOCK_ENTER_TX(pUM, idx) mutex_enter(&(pUM)->txq[(idx)].txMutex)
934 #define BNXE_LOCK_EXIT_TX(pUM, idx) mutex_exit(&(pUM)->txq[(idx)].txMutex)
935 #define BNXE_LOCK_ENTER_FREETX(pUM, idx) mutex_enter(&(pUM)->txq[(idx)].freeTxDescMutex)
936 #define BNXE_LOCK_EXIT_FREETX(pUM, idx) mutex_exit(&(pUM)->txq[(idx)].freeTxDescMutex)
H A Dbnxe_kstat.c1660 pStats->txSentPkts.value.ui64 = s_list_entry_cnt(&pUM->txq[idx].sentTxQ); in BnxeKstatTxRingUpdate()
1661 pStats->txFreeDesc.value.ui64 = s_list_entry_cnt(&pUM->txq[idx].freeTxDescQ); in BnxeKstatTxRingUpdate()
1662 pStats->txWaitingPkts.value.ui64 = s_list_entry_cnt(&pUM->txq[idx].waitTxDescQ); in BnxeKstatTxRingUpdate()
1663 pStats->txLowWater.value.ui64 = pUM->txq[idx].txLowWater; in BnxeKstatTxRingUpdate()
1664 pStats->txFailed.value.ui64 = pUM->txq[idx].txFailed; in BnxeKstatTxRingUpdate()
1665 pStats->txDiscards.value.ui64 = pUM->txq[idx].txDiscards; in BnxeKstatTxRingUpdate()
1666 pStats->txRecycle.value.ui64 = pUM->txq[idx].txRecycle; in BnxeKstatTxRingUpdate()
1667 pStats->txCopied.value.ui64 = pUM->txq[idx].txCopied; in BnxeKstatTxRingUpdate()
1668 pStats->txBlocked.value.ui64 = pUM->txq[idx].txBlocked; in BnxeKstatTxRingUpdate()
1669 pStats->txWait.value.ui64 = pUM->txq[idx].txWait; in BnxeKstatTxRingUpdate()
/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_send.c268 IN lm_tx_chain_t *txq, in lm_get_coalesce_buffer() argument
274 if (ERR_IF(CHK_NULL(pdev) || CHK_NULL(txq) || !buf_size)) { in lm_get_coalesce_buffer()
279 coalesce_buf_cnt = s_list_entry_cnt(&txq->coalesce_buf_list); in lm_get_coalesce_buffer()
283 &txq->coalesce_buf_list); in lm_get_coalesce_buffer()
294 txq->coalesce_buf_used++; in lm_get_coalesce_buffer()
298 s_list_push_tail(&txq->coalesce_buf_list, &coalesce_buf->link); in lm_get_coalesce_buffer()
315 IN lm_tx_chain_t *txq, in lm_put_coalesce_buffer() argument
318 if (ERR_IF(CHK_NULL(pdev) || CHK_NULL(txq) || CHK_NULL(coalesce_buf))) { in lm_put_coalesce_buffer()
323 s_list_push_tail(&txq->coalesce_buf_list, &coalesce_buf->link); in lm_put_coalesce_buffer()
344 IN lm_tx_chain_t *txq, in lm_copy_packet_to_coalesce_buffer() argument
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/titanic_44/usr/src/uts/common/io/yge/
H A Dyge.c2418 int32_t txq; in yge_start_port() local
2422 txq = port->p_txq; in yge_start_port()
2561 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_CLR_RESET); in yge_start_port()
2562 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_OPER_INIT); in yge_start_port()
2563 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_FIFO_OP_ON); in yge_start_port()
2564 CSR_WRITE_2(dev, Q_ADDR(txq, Q_WM), MSK_BMU_TX_WM); in yge_start_port()
2570 CSR_WRITE_2(dev, Q_ADDR(txq, Q_AL), MSK_ECU_TXFF_LEV); in yge_start_port()
2579 CSR_WRITE_4(dev, Q_ADDR(txq, Q_F), F_TX_CHK_AUTO_OFF); in yge_start_port()
2637 uint32_t txq; in yge_set_rambuffer() local
2642 txq = port->p_txq; in yge_set_rambuffer()
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/titanic_44/usr/src/uts/common/io/rwd/
H A Drt2661.c903 ring = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; in rt2661_tx_intr()
1155 rt2661_tx_dma_intr(sc, &sc->txq[0]); in rt2661_intr()
1161 rt2661_tx_dma_intr(sc, &sc->txq[1]); in rt2661_intr()
1167 rt2661_tx_dma_intr(sc, &sc->txq[2]); in rt2661_intr()
1173 rt2661_tx_dma_intr(sc, &sc->txq[3]); in rt2661_intr()
1420 ring = &sc->txq[0]; in rt2661_send()
2117 rt2661_reset_tx_ring(sc, &sc->txq[0]); in rt2661_stop_locked()
2118 rt2661_reset_tx_ring(sc, &sc->txq[1]); in rt2661_stop_locked()
2119 rt2661_reset_tx_ring(sc, &sc->txq[2]); in rt2661_stop_locked()
2120 rt2661_reset_tx_ring(sc, &sc->txq[3]); in rt2661_stop_locked()
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H A Drt2661_var.h114 struct rt2661_tx_ring txq[4]; member
/titanic_44/usr/src/uts/common/io/i40e/core/
H A Di40e_virtchnl.h234 struct i40e_virtchnl_txq_info txq; member
/titanic_44/usr/src/uts/common/io/rwn/
H A Drt2860_var.h156 struct rt2860_tx_ring txq[6]; member
H A Drt2860.c1108 ring = &sc->txq[qid]; in rt2860_send()
1660 struct rt2860_tx_ring *ring = &sc->txq[qid]; in rt2860_tx_intr()
2369 RT2860_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); in rt2860_init()
2562 rt2860_reset_tx_ring(sc, &sc->txq[qid]); in rt2860_stop()
2936 if ((err = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { in rt2860_attach()
3090 rt2860_free_tx_ring(sc, &sc->txq[qid]); in rt2860_attach()
3145 rt2860_free_tx_ring(sc, &sc->txq[qid]); in rt2860_detach()
/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/include/vm/
H A Dvfpf_if.h234 } txq; member
H A Dhw_channel.h315 } txq; member
/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/
H A Dlm_vf.c297 txq_params = &request->txq; in lm_pf_vf_fill_setup_q_response()
1927 mess->txq.txq_addr = lm_bd_chain_phys_addr(&(LM_TXQ(pdev,vf_qid).bd_chain), 0).as_u64; in lm_vf_pf_setup_q()
1928 mess->txq.vf_sb = vf_qid; in lm_vf_pf_setup_q()
1929 mess->txq.sb_index = LM_TXQ(pdev, vf_qid).hc_sb_info.hc_index_value; in lm_vf_pf_setup_q()
1931 …mess->txq.hc_rate = (u16_t)pdev->params.int_per_sec_tx[HC_PARAMS_ETH_INDEX]; /* desired … in lm_vf_pf_setup_q()
1932 mess->txq.flags |= SW_VFPF_QUEUE_FLG_HC; in lm_vf_pf_setup_q()
1987 mess->txq.txq_addr = lm_bd_chain_phys_addr(&(LM_TXQ(pdev,vf_qid).bd_chain), 0).as_u64; in lm_vf_pf_setup_q()
1988 mess->txq.vf_sb = vf_qid; in lm_vf_pf_setup_q()
1989 mess->txq.sb_index = LM_TXQ(pdev, vf_qid).hc_sb_info.hc_index_value; in lm_vf_pf_setup_q()
1991 …mess->txq.hc_rate = (u16_t)pdev->params.int_per_sec_tx[HC_PARAMS_ETH_INDEX]; /* desired … in lm_vf_pf_setup_q()
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