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Searched refs:speed_cap_mask (Results 1 – 6 of 6) sorted by relevance

/titanic_44/usr/src/uts/common/io/bnxe/
H A Dbnxe_hw.c211 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()
222 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()
233 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()
244 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()
255 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()
266 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()
277 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()
288 if (!(pLM->params.link.speed_cap_mask[i] & in BnxeHwReqPhyMediumSettings()
/titanic_44/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c454 speed_cap_mask[cfg_idx])); in elink_check_lfa()
456 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { in elink_check_lfa()
459 params->speed_cap_mask[cfg_idx]); in elink_check_lfa()
3746 params->phy[actual_phy_idx].speed_cap_mask = in set_phy_vars()
3747 params->speed_cap_mask[link_cfg_idx]; in set_phy_vars()
3760 params->phy[actual_phy_idx].speed_cap_mask); in set_phy_vars()
4060 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || in elink_warpcore_enable_AN_KR()
4070 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || in elink_warpcore_enable_AN_KR()
4133 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || in elink_warpcore_enable_AN_KR()
4778 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) in elink_sfp_e3_set_transmitter()
[all …]
/titanic_44/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc.h330 u32 speed_cap_mask; member
390 u32 speed_cap_mask[ELINK_LINK_CONFIG_SIZE]; member
/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_phy.c1465 if (pdev->params.link.speed_cap_mask[0] & PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G) in lm_init_phy()
1483 if (pdev->params.link.speed_cap_mask[0] & PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G) in lm_init_phy()
1487 else if (pdev->params.link.speed_cap_mask[0] & PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G) in lm_init_phy()
H A Dlm_devinfo.c2045 pdev->params.link.speed_cap_mask[0] = val & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; in lm_get_shmem_port_hw_config()
2049 pdev->params.link.speed_cap_mask[1] = val & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; in lm_get_shmem_port_hw_config()
2081 …( FALSE == ( pdev->params.link.speed_cap_mask[0] & (PORT_HW_CFG_SPEED_CAPABILITY_D0_10G | PORT_HW_… in lm_get_shmem_port_hw_config()
/titanic_44/usr/src/uts/common/io/bnxe/577xx/hsi/mcp/
H A Dshmem.h907 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; member