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Searched refs:scr1 (Results 1 – 21 of 21) sorted by relevance

/titanic_44/usr/src/uts/sun4u/sys/
H A Dtraptrace.h176 #define TRACE_PTR(ptr, scr1) \ argument
181 rdpr %pstate, scr1; \
182 andcc scr1, PSTATE_IE | PSTATE_AM, scr1; \
186 CPU_INDEX(scr1, ptr); \
187 sll scr1, TRAPTR_SIZE_SHIFT, scr1; \
189 add ptr, scr1, scr1; \
191 stb ptr, [scr1 + TRAPTR_ASIBUF]; \
196 ld [scr1 + TRAPTR_LIMIT], ptr; \
201 ldx [scr1 + TRAPTR_PBASE], ptr; \
202 ld [scr1 + TRAPTR_OFFSET], scr1; \
[all …]
H A Dcheetahasm.h59 #define GET_CPU_PRIVATE_PTR(off_reg, scr1, scr2, label) \ argument
60 CPU_ADDR(scr1, scr2); \
61 ldn [scr1 + CPU_PRIVATE], scr1; \
62 cmp scr1, 0; \
65 add scr1, off_reg, scr1
78 #define GET_DCACHE_DTAG(afar, datap, scr1, scr2, scr3) \ argument
86 ldxa [scr3]ASI_DC_TAG, scr1; /* read tag */ \
87 cmp scr1, scr2; \
91 stxa scr1, [datap + CH_DC_TAG]%asi; /* store tag */ \
93 ldxa [scr3]ASI_DC_UTAG, scr1; /* read utag */ \
[all …]
H A Dmachthread.h182 #define RESET_USER_RTT_REGS(scr1, scr2, label) \ argument
192 rdpr %tl, scr1; \
193 cmp scr1, 2; \
200 rdpr %tpc, scr1; \
202 cmp scr1, scr2; \
206 cmp scr1, scr2; \
212 rdpr %tstate, scr1; \
213 and scr1, TSTATE_CWP, scr1; \
221 or scr1, scr2, scr2; \
223 set user_rtt, scr1; \
[all …]
H A Dmachclock.h42 #define RD_TICK_NO_SUSPEND_CHECK(out, scr1) \ argument
47 #define RD_TICK(out, scr1, scr2, label) \ argument
48 RD_TICK_NO_SUSPEND_CHECK(out, scr1);
58 #define RD_CLOCK_TICK(out, scr1, scr2, label) \ argument
60 RD_TICK(out,scr1,scr2,label)
62 #define RD_CLOCK_TICK_NO_SUSPEND_CHECK(out, scr1) \ argument
64 RD_TICK_NO_SUSPEND_CHECK(out,scr1)
/titanic_44/usr/src/uts/sun4v/sys/
H A Dtraptrace.h233 #define TRACE_PTR(ptr, scr1) \ argument
238 rdpr %pstate, scr1; \
239 andcc scr1, PSTATE_IE | PSTATE_AM, scr1; \
243 CPU_INDEX(scr1, ptr); \
244 sll scr1, TRAPTR_SIZE_SHIFT, scr1; \
246 add ptr, scr1, scr1; \
248 stb ptr, [scr1 + TRAPTR_ASIBUF]; \
253 ld [scr1 + TRAPTR_LIMIT], ptr; \
258 ldx [scr1 + TRAPTR_PBASE], ptr; \
259 ld [scr1 + TRAPTR_OFFSET], scr1; \
[all …]
H A Dmachclock.h55 #define RD_STICK(out, scr1, scr2, label) \ argument
57 sethi %hi(native_stick_offset), scr1; \
58 ldx [scr1 + %lo(native_stick_offset)], scr2; \
60 ldx [scr1 + %lo(native_stick_offset)], scr1; \
61 sub scr1, scr2, scr2; \
66 add out, scr1, out
79 #define RD_CLOCK_TICK(out, scr1, scr2, label) \ argument
81 RD_STICK(out,scr1,scr2,label)
83 #define RD_STICK_NO_SUSPEND_CHECK(out, scr1) \ argument
84 sethi %hi(native_stick_offset), scr1; \
[all …]
/titanic_44/usr/src/uts/sparc/v7/sys/
H A Dtraptrace.h102 #define TRACE_PTR(ptr, scr1) \ argument
103 CPU_INDEX(scr1); \
104 sll scr1, TRAPTR_SIZE_SHIFT, scr1; \
106 ld [ptr + scr1], ptr; \
107 set panicstr, scr1; \
108 ld [scr1], scr1; \
109 tst scr1; \
111 sethi %hi(trap_tr_panic), scr1; \
112 or scr1, %lo(trap_tr_panic), ptr
119 #define TRACE_NEXT(ptr, scr1, scr2) \ argument
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/titanic_44/usr/src/uts/intel/ia32/sys/
H A Dtraptrace.h116 #define TRACE_PTR(ptr, scr1, scr1_32, scr2, marker) \
122 shlq $TRAPTR_SIZE_SHIFT, scr1; \
124 addq scr2, scr1; \
125 movq TRAPTR_NEXT(scr1), ptr; \
127 cmpq TRAPTR_LIMIT(scr1), scr2; \
129 movq TRAPTR_FIRST(scr1), scr2; \
130 8: movq scr2, TRAPTR_NEXT(scr1); \
135 #define TRACE_PTR(ptr, scr1, scr1_32, scr2, marker) \
141 shll $TRAPTR_SIZE_SHIFT, scr1; \
142 addl $trap_trace_ctl, scr1; \
[all …]
/titanic_44/usr/src/uts/sun4v/vm/
H A Dmach_sfmmu.h87 #define TSTAT_CHECK_TL1(label, scr1, scr2) \ argument
88 rdpr %tpc, scr1; \
91 cmp scr1, scr2; \
150 #define GET_MMU_D_TAGACC(tagacc, scr1) \ argument
151 GET_MMU_D_PTAGACC_CTXTYPE(tagacc, scr1)
161 #define GET_MMU_D_TTARGET(ttarget, scr1) \ argument
163 ldx [ttarget + MMFSA_D_CTX], scr1; \
164 sllx scr1, TTARGET_CTX_SHIFT, scr1; \
167 or ttarget, scr1, ttarget
179 #define GET_MMU_BOTH_TAGACC(dtagacc, itagacc, scr1, scr2) \ argument
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/titanic_44/usr/src/uts/sun4/sys/
H A Dclock.h244 #define NATIVE_TIME_TO_NSEC_SCALE(out, scr1, scr2, shift) \ argument
248 mulx out, scr1, out; /* delay: 32-bit fast path */ \
251 mulx scr2, scr1, scr2; /* scr2 = (H*F) */ \
253 mulx out, scr1, scr1; /* scr1 = (L*F) */ \
254 srlx scr1, 32, scr1; /* scr1 = (L*F) >> 32 */ \
256 add scr1, scr2, out; /* out = (H*F) + ((L*F) >> 32) */\
261 #define NATIVE_TIME_TO_NSEC(out, scr1, scr2) \ argument
262 sethi %hi(nsec_scale), scr1; /* load scaling factor */ \
263 ld [scr1 + %lo(nsec_scale)], scr1; \
264 NATIVE_TIME_TO_NSEC_SCALE(out, scr1, scr2, NSEC_SHIFT);
/titanic_44/usr/src/uts/sun4u/cpu/
H A Dus3_jalapeno_asm.s108 #define SET_JP_SPEED(speed, scr1, scr2) \ argument
109 ldxa [%g0]ASI_JBUS_CONFIG, scr1; \
111 andn scr1, scr2, scr1; \
113 or scr1, scr2, scr1; \
114 stxa scr1, [%g0]ASI_JBUS_CONFIG;
135 #define SET_SLAVE_T_SPEED(speed, scr1, scr2) \ argument
141 SET_64BIT_PA(scr1, scr2, TOM_HIGH_PA, S_T_ESTAR_CTRL_PA); \
142 SET_TOM_SPEED(speed, scr1, scr2); \
153 #define JP_ADJUST_FSM(value, scr1, scr2) \ argument
154 ldxa [%g0]ASI_MCU_CTRL, scr1; \
[all …]
H A Dus3_cheetah_asm.s67 #define ECACHE_FLUSH_LINE(physaddr, ecache_size, scr1, scr2) \ argument
68 xor physaddr, ecache_size, scr1; \
71 and scr1, scr2, scr1; \
73 add scr1, scr2, scr1; \
74 ECACHE_REFLUSH_LINE(ecache_size, scr1, scr2)
H A Dopl_olympus_asm.s621 #define OPL_TRAPTRACE(ptr, scr1, scr2, label) \ argument
622 CPU_INDEX(scr1, ptr); \
623 sll scr1, TRAPTR_SIZE_SHIFT, scr1; \
625 add ptr, scr1, scr1; \
626 ld [scr1 + TRAPTR_LIMIT], ptr; \
629 ldx [scr1 + TRAPTR_PBASE], ptr; \
630 ld [scr1 + TRAPTR_OFFSET], scr1; \
631 add ptr, scr1, ptr; \
634 rd STICK, scr1; \
635 stxa scr1, [ptr + TRAP_ENT_TICK]%asi; \
[all …]
H A Dus3_cheetahplus_asm.s80 #define ECACHE_FLUSH_LINE(physaddr, ec_set_size, scr1, scr2) \ argument
81 sub ec_set_size, 1, scr1; \
82 and physaddr, scr1, scr1; \
84 or scr2, scr1, scr1; \
85 ECACHE_REFLUSH_LINE(ec_set_size, scr1, scr2)
H A Dcommon_asm.s54 #define GET_NATIVE_TIME(out, scr1, scr2) \ argument
56 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \ argument
62 #define WR_TICKCMPR(in, scr1, scr2, label) \ argument
184 #define GET_NATIVE_TIME(out, scr1, scr2) \ argument
186 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \ argument
201 #define WR_TICKCMPR(cmpr,scr1,scr2,label) \ argument
208 #define WR_TICKCMPR(in,scr1,scr2,label) \ argument
H A Dspitfire_asm.s317 #define GET_CPU_PRIVATE_PTR(r_or_s, scr1, scr2, label) \ argument
318 CPU_ADDR(scr1, scr2); \
319 ldn [scr1 + CPU_PRIVATE], scr1; \
320 cmp scr1, 0; \
323 add scr1, r_or_s, scr1; \
/titanic_44/usr/src/uts/sun4u/vm/
H A Dmach_sfmmu.h120 #define TSTAT_CHECK_TL1(label, scr1, scr2) \ argument
121 rdpr %tpc, scr1; \
124 cmp scr1, scr2; \
164 #define GET_MMU_D_TAGACC(tagacc, scr1) \ argument
165 mov MMU_TAG_ACCESS, scr1; \
166 ldxa [scr1]ASI_DMMU, tagacc
176 #define GET_MMU_D_TTARGET(ttarget, scr1) \ argument
188 #define GET_MMU_BOTH_TAGACC(dtagacc, itagacc, scr1, scr2) \ argument
189 mov MMU_TAG_ACCESS, scr1; \
190 ldxa [scr1]ASI_DMMU, dtagacc; \
[all …]
/titanic_44/usr/src/cmd/mdb/sparc/v9/kmdb/
H A Dkaif_handlers.s103 #define KAIF_ITLB_STUFF(tte, ouch, scr1, scr2, scr3, scr4) \ argument
104 mov %o0, scr1; \
120 mov scr1, %o0; \
136 #define KAIF_DTLB_STUFF(tte, ouch, scr1, scr2, scr3, scr4) \ argument
137 mov %o0, scr1; \
153 mov scr1, %o0; \
171 #define KAIF_DTLB_STUFF(tte, ouch, scr1, scr2, scr3, scr4) \ argument
172 DTLB_STUFF(tte, scr1, scr2, scr3, scr4)
174 #define KAIF_ITLB_STUFF(tte, ouch, scr1, scr2, scr3, scr4) \ argument
175 ITLB_STUFF(tte, scr1, scr2, scr3, scr4)
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/titanic_44/usr/src/cmd/mdb/sun4v/v9/kmdb/
H A Dmach_asmutil.h38 #define GET_NWIN(scr1, reg1) \ argument
39 rdpr %cwp, scr1; /* save current %cwp */ \
42 wrpr %g0, scr1, %cwp /* restore current %cwp */
/titanic_44/usr/src/cmd/mdb/sun4u/v9/kmdb/
H A Dmach_asmutil.h38 #define GET_NWIN(scr1, reg1) \ argument
/titanic_44/usr/src/lib/libc/sparcv9/gen/
H A Dstrcmp.s131 cmp %o3, %g1 ! *scr1 == *src2 ?