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Searched refs:sc_cfg_base (Results 1 – 14 of 14) sorted by relevance

/titanic_44/usr/src/uts/common/io/rwd/
H A Drt2661_var.h103 caddr_t sc_cfg_base; member
H A Drt2661.c2853 err = ddi_regs_map_setup(devinfo, 0, &sc->sc_cfg_base, 0, 0, in rt2661_attach()
2862 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ)); in rt2661_attach()
2869 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_VENID)); in rt2661_attach()
2871 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_DEVID)); in rt2661_attach()
2882 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_COMM), in rt2661_attach()
2885 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_LATENCY_TIMER), 0xa8); in rt2661_attach()
2887 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_ILINE), 0x10); in rt2661_attach()
/titanic_44/usr/src/uts/common/io/iwk/
H A Diwk2_var.h167 caddr_t sc_cfg_base; member
H A Diwk2.c521 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0, in iwk_attach()
529 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_REVID)); in iwk_attach()
530 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0x41), 0); in iwk_attach()
532 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ)); in iwk_attach()
4026 (uint32_t *)(sc->sc_cfg_base + 0xe8)); in iwk_preinit()
4028 (uint32_t *)(sc->sc_cfg_base + 0xe8), in iwk_preinit()
4034 (uint8_t *)(sc->sc_cfg_base + 0xf0)); in iwk_preinit()
4035 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0xf0), in iwk_preinit()
/titanic_44/usr/src/uts/common/io/rwn/
H A Drt2860_var.h131 caddr_t sc_cfg_base; member
H A Drt2860.c2856 err = ddi_regs_map_setup(devinfo, 0, &sc->sc_cfg_base, 0, 0, in rt2860_attach()
2865 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ)); in rt2860_attach()
2872 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_VENID)); in rt2860_attach()
2874 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_DEVID)); in rt2860_attach()
2885 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_COMM), in rt2860_attach()
2888 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_LATENCY_TIMER), 0xa8); in rt2860_attach()
2890 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_ILINE), 0x10); in rt2860_attach()
/titanic_44/usr/src/uts/common/io/iwh/
H A Diwh_var.h172 caddr_t sc_cfg_base; member
H A Diwh.c560 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0, in iwh_attach()
569 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID)); in iwh_attach()
587 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_REVID)); in iwh_attach()
592 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + in iwh_attach()
599 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ)); in iwh_attach()
4644 (uint32_t *)(sc->sc_cfg_base + 0xe8)); in iwh_preinit()
4646 (uint32_t *)(sc->sc_cfg_base + 0xe8), in iwh_preinit()
4651 (uint8_t *)(sc->sc_cfg_base + 0xf0)); in iwh_preinit()
4652 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0xf0), in iwh_preinit()
/titanic_44/usr/src/uts/common/io/iwp/
H A Diwp_var.h190 caddr_t sc_cfg_base; member
H A Diwp.c520 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0, in iwp_attach()
529 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID)); in iwp_attach()
544 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_REVID)); in iwp_attach()
549 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + in iwp_attach()
556 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ)); in iwp_attach()
4370 (uint32_t *)(sc->sc_cfg_base + 0xe8)); in iwp_preinit()
4372 (uint32_t *)(sc->sc_cfg_base + 0xe8), in iwp_preinit()
4377 (uint8_t *)(sc->sc_cfg_base + 0xf0)); in iwp_preinit()
4378 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0xf0), in iwp_preinit()
/titanic_44/usr/src/uts/common/io/rtw/
H A Drtwvar.h418 caddr_t sc_cfg_base; member
H A Drtw.c3164 err = ddi_regs_map_setup(devinfo, 0, (caddr_t *)&rsc->sc_cfg_base, 0, 0, in rtw_attach()
3172 (uint8_t *)(rsc->sc_cfg_base + PCI_CONF_CACHE_LINESZ)); in rtw_attach()
3177 (uint16_t *)((uintptr_t)rsc->sc_cfg_base + PCI_CONF_VENID)); in rtw_attach()
3179 (uint16_t *)((uintptr_t)rsc->sc_cfg_base + PCI_CONF_DEVID)); in rtw_attach()
3189 (uint16_t *)((uintptr_t)rsc->sc_cfg_base + PCI_CONF_COMM), command); in rtw_attach()
3194 (uint8_t *)(rsc->sc_cfg_base + PCI_CONF_LATENCY_TIMER), 0xa8); in rtw_attach()
/titanic_44/usr/src/uts/common/io/mwl/
H A Dmwl.c3849 err = ddi_regs_map_setup(devinfo, 0, (caddr_t *)&sc->sc_cfg_base, 0, 0, in mwl_attach()
3857 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ)); in mwl_attach()
3863 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_VENID)); in mwl_attach()
3865 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID)); in mwl_attach()
3876 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_COMM), in mwl_attach()
3879 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_LATENCY_TIMER), 0xa8); in mwl_attach()
3881 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_ILINE), 0x10); in mwl_attach()
H A Dmwl_var.h498 caddr_t sc_cfg_base; member