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Searched refs:rxq (Results 1 – 25 of 28) sorted by relevance

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/titanic_44/usr/src/uts/common/io/cxgbe/t4nex/
H A Dadapter.h379 struct sge_rxq *rxq; /* NIC rx queues */ member
529 #define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq) argument
530 #define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq) argument
531 #define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq) argument
532 #define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq) argument
534 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) argument
535 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) argument
536 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) argument
537 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) argument
552 #define for_each_rxq(pi, iter, rxq) \ argument
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H A Dt4_sge.c87 static int alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx,
89 static int free_rxq(struct port_info *pi, struct sge_rxq *rxq);
157 static kstat_t *setup_rxq_kstats(struct port_info *pi, struct sge_rxq *rxq,
401 iq = &s->rxq[pi->first_rxq + idx].iq; in port_intr_iq()
407 iq = &s->rxq[pi->first_rxq + idx].iq; in port_intr_iq()
419 iq = &s->rxq[pi->first_rxq + idx].iq; in port_intr_iq()
429 struct sge_rxq *rxq; in t4_setup_port_queues() local
451 for_each_rxq(pi, i, rxq) { in t4_setup_port_queues()
453 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, p->qsize_rxq, in t4_setup_port_queues()
456 init_fl(&rxq->fl, p->qsize_rxq / 8); /* 8 bufs in each entry */ in t4_setup_port_queues()
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H A Dt4_nexus.c506 s->rxq = kmem_zalloc(s->nrxq * sizeof (struct sge_rxq), KM_SLEEP); in t4_devo_attach()
607 struct sge_rxq *rxq; in t4_devo_attach() local
619 rxq = &s->rxq[pi->first_rxq]; in t4_devo_attach()
620 for (q = 0; q < pi->nrxq; q++, rxq++) { in t4_devo_attach()
623 &rxq->iq); in t4_devo_attach()
718 if (s->rxq != NULL) in t4_devo_detach()
719 kmem_free(s->rxq, s->nrxq * sizeof (struct sge_rxq)); in t4_devo_detach()
2026 struct sge_rxq *rxq; in port_full_init() local
2043 for_each_rxq(pi, i, rxq) { in port_full_init()
2044 rss[i] = rxq->iq.abs_id; in port_full_init()
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H A Dt4_mac.c1002 struct sge_rxq *rxq; in setprop() local
1021 for_each_rxq(pi, i, rxq) { in setprop()
1022 rxq->iq.intr_params = V_QINTR_TIMER_IDX(v) | in setprop()
1034 for_each_rxq(pi, i, rxq) { in setprop()
1035 rxq->iq.intr_params = V_QINTR_TIMER_IDX(pi->tmr_idx) | in setprop()
1039 rxq->iq.intr_pktc_idx = v; /* this needs fresh plumb */ in setprop()
1144 t4_mac_rx(struct port_info *pi, struct sge_rxq *rxq, mblk_t *m) in t4_mac_rx() argument
/titanic_44/usr/src/uts/common/io/bnxe/
H A Dbnxe_rx.c77 if (pUM->rxq[idx].rxLowWater > s_list_entry_cnt(&pLmRxChain->active_descq)) in BnxeRxPostBuffers()
79 pUM->rxq[idx].rxLowWater = s_list_entry_cnt(&pLmRxChain->active_descq); in BnxeRxPostBuffers()
182 s_list_push_tail(&pUM->rxq[idx].doneRxQ, in BnxeRxPktFree()
186 if (s_list_entry_cnt(&pUM->rxq[idx].doneRxQ) >= pUM->devParams.maxRxFree) in BnxeRxPktFree()
188 doneRxQ = pUM->rxq[idx].doneRxQ; in BnxeRxPktFree()
189 s_list_clear(&pUM->rxq[idx].doneRxQ); in BnxeRxPktFree()
200 atomic_dec_32(&pUM->rxq[idx].rxBufUpInStack); in BnxeRxPktFree()
215 if ((cnt = pUM->rxq[FCOE_CID(&pUM->lm_dev)].rxBufUpInStack) == 0) in BnxeWaitForPacketsFromClient()
241 if ((cnt = pUM->rxq[idx].rxBufUpInStack) == 0) in BnxeWaitForPacketsFromClient()
298 pRxQ = &pUM->rxq[idx]; in BnxeRxRingProcess()
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H A Dbnxe_lock.c47 void BNXE_LOCK_ENTER_RX (um_device_t * pUM, int idx) { mutex_enter(&pUM->rxq[idx].rxMut… in BNXE_LOCK_ENTER_RX()
48 void BNXE_LOCK_EXIT_RX (um_device_t * pUM, int idx) { mutex_exit(&pUM->rxq[idx].rxMute… in BNXE_LOCK_EXIT_RX()
49 void BNXE_LOCK_ENTER_DONERX (um_device_t * pUM, int idx) { mutex_enter(&pUM->rxq[idx].doneR… in BNXE_LOCK_ENTER_DONERX()
50 void BNXE_LOCK_EXIT_DONERX (um_device_t * pUM, int idx) { mutex_exit(&pUM->rxq[idx].doneRx… in BNXE_LOCK_EXIT_DONERX()
H A Dbnxe_main.c240 mutex_init(&pUM->rxq[idx].rxMutex, NULL, in BnxeMutexInit()
242 mutex_init(&pUM->rxq[idx].doneRxMutex, NULL, in BnxeMutexInit()
244 pUM->rxq[idx].pUM = pUM; in BnxeMutexInit()
245 pUM->rxq[idx].idx = idx; in BnxeMutexInit()
310 mutex_destroy(&pUM->rxq[idx].rxMutex); in BnxeMutexDestroy()
311 mutex_destroy(&pUM->rxq[idx].doneRxMutex); in BnxeMutexDestroy()
H A Dbnxe.h660 RxQueue rxq[MAX_ETH_CONS]; member
937 #define BNXE_LOCK_ENTER_RX(pUM, idx) mutex_enter(&(pUM)->rxq[(idx)].rxMutex)
938 #define BNXE_LOCK_EXIT_RX(pUM, idx) mutex_exit(&(pUM)->rxq[(idx)].rxMutex)
939 #define BNXE_LOCK_ENTER_DONERX(pUM, idx) mutex_enter(&(pUM)->rxq[(idx)].doneRxMutex)
940 #define BNXE_LOCK_EXIT_DONERX(pUM, idx) mutex_exit(&(pUM)->rxq[(idx)].doneRxMutex)
H A Dbnxe_kstat.c1614 pStats->rxDoneDescs.value.ui64 = s_list_entry_cnt(&pUM->rxq[idx].doneRxQ); in BnxeKstatRxRingUpdate()
1615 pStats->rxWaitingDescs.value.ui64 = s_list_entry_cnt(&pUM->rxq[idx].waitRxQ); in BnxeKstatRxRingUpdate()
1616 pStats->rxCopied.value.ui64 = pUM->rxq[idx].rxCopied; in BnxeKstatRxRingUpdate()
1617 pStats->rxDiscards.value.ui64 = pUM->rxq[idx].rxDiscards; in BnxeKstatRxRingUpdate()
1618 pStats->rxBufUpInStack.value.ui64 = pUM->rxq[idx].rxBufUpInStack; in BnxeKstatRxRingUpdate()
1619 pStats->rxLowWater.value.ui64 = pUM->rxq[idx].rxLowWater; in BnxeKstatRxRingUpdate()
1620 pStats->inPollMode.value.ui64 = pUM->rxq[idx].inPollMode; in BnxeKstatRxRingUpdate()
1621 pStats->pollCnt.value.ui64 = pUM->rxq[idx].pollCnt; in BnxeKstatRxRingUpdate()
1622 pStats->intrDisableCnt.value.ui64 = pUM->rxq[idx].intrDisableCnt; in BnxeKstatRxRingUpdate()
1623 pStats->intrEnableCnt.value.ui64 = pUM->rxq[idx].intrEnableCnt; in BnxeKstatRxRingUpdate()
[all …]
H A Dbnxe_intr.c151 RxQueue * pRxQ = &pUM->rxq[idx]; in BnxeIntrIguSbEnable()
193 RxQueue * pRxQ = &pUM->rxq[idx]; in BnxeIntrIguSbDisable()
758 if (pUM->rxq[idx].inPollMode) in BnxeIntrMISR()
H A Dbnxe_fcoe.c1337 RxQueue * pRxQ = &pUM->rxq[FCOE_CID(&pUM->lm_dev)]; in BnxeFcoePrvPoll()
/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_recv.c1253 lm_rx_chain_t *rxq = &LM_RXQ(pdev, qidx); in lm_return_packet_bytes() local
1255 rxq->ret_bytes += returned_bytes; in lm_return_packet_bytes()
1265 if(S32_SUB(rxq->ret_bytes, rxq->ret_bytes_last_fw_update + HC_RET_BYTES_TH(pdev)) >= 0) in lm_return_packet_bytes()
1275 …LM_INTMEM_WRITE32(PFDEV(pdev), rxq->hc_sb_info.iro_dhc_offset, rxq->ret_bytes, BAR_CSTRORM_INTMEM); in lm_return_packet_bytes()
1276 rxq->ret_bytes_last_fw_update = rxq->ret_bytes; in lm_return_packet_bytes()
1278 … VF_REG_WR(pdev, VF_BAR0_CSDM_QUEUES_OFFSET + rxq->hc_sb_info.iro_dhc_offset, rxq->ret_bytes); in lm_return_packet_bytes()
1279 rxq->ret_bytes_last_fw_update = rxq->ret_bytes; in lm_return_packet_bytes()
/titanic_44/usr/src/uts/common/io/ral/
H A Drt2560.c691 RAL_WRITE(sc, RT2560_RXCSR2, sc->rxq.physaddr); in rt2560_ring_hwsetup()
1189 dr = &sc->rxq.dr_desc; in rt2560_rx_intr()
1190 count = sc->rxq.count; in rt2560_rx_intr()
1192 mutex_enter(&sc->rxq.rx_lock); in rt2560_rx_intr()
1198 desc = &sc->rxq.desc[sc->rxq.cur]; in rt2560_rx_intr()
1199 data = &sc->rxq.data[sc->rxq.cur]; in rt2560_rx_intr()
1245 dr_bf = &sc->rxq.dr_rxbuf[sc->rxq.cur]; in rt2560_rx_intr()
1266 ral_debug(RAL_DBG_RX, "rx done idx=%u\n", sc->rxq.cur); in rt2560_rx_intr()
1268 sc->rxq.cur = (sc->rxq.cur + 1) % RT2560_RX_RING_COUNT; in rt2560_rx_intr()
1270 mutex_exit(&sc->rxq.rx_lock); in rt2560_rx_intr()
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H A Drt2560_var.h164 struct rt2560_rx_ring rxq; member
/titanic_44/usr/src/uts/common/io/yge/
H A Dyge.c2417 int32_t rxq; in yge_start_port() local
2423 rxq = port->p_rxq; in yge_start_port()
2584 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_CLR_RESET); in yge_start_port()
2585 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_OPER_INIT); in yge_start_port()
2586 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_FIFO_OP_ON); in yge_start_port()
2588 CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), 0x80); in yge_start_port()
2590 CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), MSK_BMU_RX_WM); in yge_start_port()
2595 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); in yge_start_port()
2601 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), in yge_start_port()
2636 uint32_t rxq; in yge_set_rambuffer() local
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/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/
H A Dlm_vf.c280 rxq_params = &request->rxq; in lm_pf_vf_fill_setup_q_response()
1895 mess->rxq.rcq_addr = lm_bd_chain_phys_addr(&(LM_RCQ(pdev,vf_qid).bd_chain), 0).as_u64; in lm_vf_pf_setup_q()
1896 mess->rxq.rcq_np_addr = lm_bd_chain_phys_addr(&(LM_RCQ(pdev,vf_qid).bd_chain), 1).as_u64; in lm_vf_pf_setup_q()
1897 mess->rxq.rxq_addr = lm_bd_chain_phys_addr(&(LM_RXQ_CHAIN(pdev,vf_qid,0)), 0).as_u64; in lm_vf_pf_setup_q()
1899 mess->rxq.sge_addr = LM_TPA_CHAIN_BD(pdev, vf_qid).bd_chain_phy.as_u64; in lm_vf_pf_setup_q()
1900 if (mess->rxq.sge_addr) { in lm_vf_pf_setup_q()
1901 mess->rxq.flags |= SW_VFPF_QUEUE_FLG_TPA; in lm_vf_pf_setup_q()
1904 mess->rxq.sge_addr = 0; in lm_vf_pf_setup_q()
1908 mess->rxq.vf_sb = vf_qid; /* relative to vf */ in lm_vf_pf_setup_q()
1909 mess->rxq.flags |= SW_VFPF_QUEUE_FLG_CACHE_ALIGN; in lm_vf_pf_setup_q()
[all …]
/titanic_44/usr/src/uts/common/io/rwn/
H A Drt2860.c1717 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; in rt2860_rx_intr()
1718 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; in rt2860_rx_intr()
1721 (void) ddi_dma_sync(sc->rxq.rxdesc_dma.dma_hdl, in rt2860_rx_intr()
1722 sc->rxq.cur * sizeof (struct rt2860_rxd), in rt2860_rx_intr()
1788 (void) ddi_dma_sync(sc->rxq.rxdesc_dma.dma_hdl, in rt2860_rx_intr()
1789 sc->rxq.cur * sizeof (struct rt2860_rxd), in rt2860_rx_intr()
1793 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; in rt2860_rx_intr()
1799 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); in rt2860_rx_intr()
2375 RT2860_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); in rt2860_init()
2563 rt2860_reset_rx_ring(sc, &sc->rxq); in rt2860_stop()
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H A Drt2860_var.h157 struct rt2860_rx_ring rxq; member
/titanic_44/usr/src/uts/common/io/i40e/core/
H A Di40e_virtchnl.h235 struct i40e_virtchnl_rxq_info rxq; member
/titanic_44/usr/src/uts/common/io/rwd/
H A Drt2661_var.h116 struct rt2661_rx_ring rxq; member
H A Drt2661.c976 ring = &sc->rxq; in rt2661_rx_intr()
1056 "rx intr idx=%u\n", sc->rxq.cur); in rt2661_rx_intr()
2122 rt2661_reset_rx_ring(sc, &sc->rxq); in rt2661_stop_locked()
2441 RT2661_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.paddr); in rt2661_init()
3004 err = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); in rt2661_attach()
3144 rt2661_free_rx_ring(sc, &sc->rxq); in rt2661_attach()
3216 rt2661_free_rx_ring(sc, &sc->rxq); in rt2661_detach()
/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/include/vm/
H A Dvfpf_if.h219 } rxq; member
H A Dhw_channel.h300 } rxq; member
/titanic_44/usr/src/uts/common/io/fibre-channel/fca/emlxs/
H A Demlxs_sli4.c5801 RXQ_DESC_t *rxq; in emlxs_sli4_rxq_get() local
5805 rxq = &hba->sli.sli4.rxq[EMLXS_RXQ_ELS]; in emlxs_sli4_rxq_get()
5808 rxq = &hba->sli.sli4.rxq[EMLXS_RXQ_CT]; in emlxs_sli4_rxq_get()
5814 mutex_enter(&rxq->lock); in emlxs_sli4_rxq_get()
5816 q = &rxq->active; in emlxs_sli4_rxq_get()
5846 mutex_exit(&rxq->lock); in emlxs_sli4_rxq_get()
5859 RXQ_DESC_t *rxq; in emlxs_sli4_rxq_put() local
5865 rxq = &hba->sli.sli4.rxq[EMLXS_RXQ_ELS]; in emlxs_sli4_rxq_put()
5868 rxq = &hba->sli.sli4.rxq[EMLXS_RXQ_CT]; in emlxs_sli4_rxq_put()
5874 mutex_enter(&rxq->lock); in emlxs_sli4_rxq_put()
[all …]
/titanic_44/usr/src/uts/common/io/cxgbe/common/
H A Dcommon.h450 unsigned int rxqi, unsigned int rxq, unsigned int tc, unsigned int vi,

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