| /titanic_44/usr/src/uts/sun4/io/px/ |
| H A D | px_mmu.c | 181 px_dvma_addr_t pg_index = MMU_PAGE_INDEX(mmu_p, dvma_pg); in px_mmu_map_pages() local
187 (uint_t)pg_index, dvma_pg, (uint_t)npages, (uint_t)pfn_index); in px_mmu_map_pages()
189 if (px_lib_iommu_map(dip, PCI_TSBID(0, pg_index), npages, in px_mmu_map_pages()
202 pg_index + npages); in px_mmu_map_pages()
206 if (px_lib_iommu_map(dip, PCI_TSBID(0, pg_index + npages), 1, in px_mmu_map_pages()
212 if (px_lib_iommu_demap(dip, PCI_TSBID(0, pg_index), npages) in px_mmu_map_pages()
231 px_dvma_addr_t pg_index = MMU_PAGE_INDEX(mmu_p, dvma_pg); in px_mmu_unmap_pages() local
235 (uint_t)mmu_p->dvma_base_pg, (uint_t)pg_index, dvma_pg, in px_mmu_unmap_pages()
239 PCI_TSBID(0, pg_index), npages) != DDI_SUCCESS) { in px_mmu_unmap_pages()
248 "redzone pg=%x\n", pg_index + npages); in px_mmu_unmap_pages()
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| H A D | px_fdvma.c | 59 size_t npages, pg_index; in px_fdvma_load() local
80 pg_index = dvma_pg - mmu_p->dvma_base_pg; in px_fdvma_load()
89 if (px_lib_iommu_map(dip, PCI_TSBID(0, pg_index), npages, in px_fdvma_load()
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| /titanic_44/usr/src/uts/sun4u/io/pci/ |
| H A D | pci_iommu.c | 266 dvma_addr_t pg_index = dvma_pg - iommu_p->dvma_base_pg; in iommu_map_pages() local
267 uint64_t *tte_addr = iommu_p->iommu_tsb_vaddr + pg_index; in iommu_map_pages()
278 (uint_t)iommu_p->dvma_base_pg, (uint_t)pg_index, dvma_pg, in iommu_map_pages()
281 for (i = pfn_index; i < pfn_last; i++, pg_index++, tte_addr++) { in iommu_map_pages()
289 pg_index, HI32(cur_tte), LO32(cur_tte)); in iommu_map_pages()
299 ASSERT(tte_addr == iommu_p->iommu_tsb_vaddr + pg_index); in iommu_map_pages()
303 pg_index); in iommu_map_pages()
304 ASSERT(TTE_IS_INVALID(iommu_p->iommu_tsb_vaddr[pg_index])); in iommu_map_pages()
347 dvma_addr_t pg_index = IOMMU_PAGE_INDEX(iommu_p, dvma_pg); in iommu_unmap_pages() local
349 for (; npages; npages--, dvma_pg++, pg_index++) { in iommu_unmap_pages()
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| H A D | pci_fdvma.c | 60 size_t npages, pg_index; in pci_fdvma_load() local
86 pg_index = dvma_pg - iommu_p->dvma_base_pg; in pci_fdvma_load()
112 iommu_p->iommu_tsb_vaddr[pg_index + i] = tte | IOMMU_PTOB(pfn); in pci_fdvma_load()
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| H A D | pci_reloc.c | 223 dvma_addr_t pg_index = dvma_pg - iommu_p->dvma_base_pg; in pci_fdvma_remap() local
241 iommu_p->iommu_tsb_vaddr[pg_index + i]); in pci_fdvma_remap()
250 iommu_p->iommu_tsb_vaddr[pg_index + i] = tte | IOMMU_PTOB(pfn); in pci_fdvma_remap()
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| /titanic_44/usr/src/uts/sun4u/sys/pci/ |
| H A D | pci_iommu.h | 211 #define IOMMU_UNLOAD_TTE(iommu_p, pg_index) \ argument
212 (iommu_p)->iommu_tsb_vaddr[pg_index] = COMMON_IOMMU_INVALID_TTE
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| /titanic_44/usr/src/uts/sun4u/io/px/ |
| H A D | px_lib4u.c | 721 px_dvma_addr_t pg_index; in px_lib_msiq_init() local
754 pg_index = MMU_PAGE_INDEX(px_p->px_mmu_p, in px_lib_msiq_init()
757 if ((ret = px_lib_iommu_map(px_p->px_dip, PCI_TSBID(0, pg_index), in px_lib_msiq_init()
787 px_dvma_addr_t pg_index; in px_lib_msiq_fini() local
799 pg_index = MMU_PAGE_INDEX(px_p->px_mmu_p, in px_lib_msiq_fini()
803 PCI_TSBID(0, pg_index), MMU_BTOP(size)); in px_lib_msiq_fini()
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| /titanic_44/usr/src/uts/i86pc/vm/ |
| H A D | hat_i86.c | 2278 pgcnt_t pg_index; in hat_kmap_unload() local
2288 pg_index = mmu_btop(va - mmu.kmap_addr); in hat_kmap_unload()
2289 pte_ptr = PT_INDEX_PTR(mmu.kmap_ptes, pg_index); in hat_kmap_unload()
2814 pgcnt_t pg_index; in hat_getpfnum() local
2816 pg_index = mmu_btop(vaddr - mmu.kmap_addr); in hat_getpfnum()
2817 pte = GET_PTE(PT_INDEX_PTR(mmu.kmap_ptes, pg_index)); in hat_getpfnum()
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