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Searched refs:pci_size_low (Results 1 – 25 of 42) sorted by relevance

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/titanic_44/usr/src/uts/intel/io/pciex/
H A Dpcie_nvidia.c233 regs[0].pci_size_low = assigned[0].pci_size_low = PCI_CONF_HDR_SIZE; in add_nvidia_isa_bridge_props()
242 regs[1].pci_size_low = assigned[1].pci_size_low = PCI_CONF_HDR_SIZE; in add_nvidia_isa_bridge_props()
/titanic_44/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c1435 space_type, assigned[i].pci_phys_low, assigned[i].pci_size_low); in pcicfg_get_ntbridge_child_range()
1439 *boundlen = assigned[i].pci_size_low; in pcicfg_get_ntbridge_child_range()
1878 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { in pcicfg_bridge_assign()
1888 reg[i].pci_size_low, &mem_answer); in pcicfg_bridge_assign()
1891 reg[i].pci_size_low, &mem_answer); in pcicfg_bridge_assign()
1909 reg[i].pci_size_low, &mem_answer); in pcicfg_bridge_assign()
1913 reg[i].pci_size_low, &mem_answer); in pcicfg_bridge_assign()
1929 (void) pcicfg_get_io(entry, reg[i].pci_size_low, in pcicfg_bridge_assign()
2037 if ((reg[i].pci_size_low != 0)|| (reg[i].pci_size_hi != 0)) { in pcicfg_device_assign()
2040 request.ra_len = reg[i].pci_size_low; in pcicfg_device_assign()
[all …]
/titanic_44/usr/src/uts/sun4/io/
H A Dpcicfg.c1530 space_type, assigned[i].pci_phys_low, assigned[i].pci_size_low); in pcicfg_get_ntbridge_child_range()
1534 *boundlen = assigned[i].pci_size_low; in pcicfg_get_ntbridge_child_range()
1981 if ((reg[i].pci_size_low != 0)|| in pcicfg_bridge_assign()
1990 reg[i].pci_size_low, &mem_answer); in pcicfg_bridge_assign()
2009 reg[i].pci_size_low, &mem_answer); in pcicfg_bridge_assign()
2024 reg[i].pci_size_low, &io_answer); in pcicfg_bridge_assign()
2126 if ((reg[i].pci_size_low != 0)|| in pcicfg_device_assign()
2130 request.ra_len = reg[i].pci_size_low; in pcicfg_device_assign()
2294 if ((assigned[i].pci_size_low != 0)|| in pcicfg_device_assign_readonly()
2297 request.ra_len = assigned[i].pci_size_low; in pcicfg_device_assign_readonly()
[all …]
/titanic_44/usr/src/uts/common/io/
H A Dbusra.c1042 (uint64_t)regs[i].pci_size_low, in pci_resource_setup()
1053 ((uint64_t)(regs[i].pci_size_low)), in pci_resource_setup()
1062 (uint64_t)regs[i].pci_size_low, in pci_resource_setup()
1231 (uint64_t)avail_p->pci_size_low, in pci_resource_setup_avail()
1239 (uint64_t)avail_p->pci_size_low, NDI_RA_TYPE_IO, 0); in pci_resource_setup_avail()
1362 ((uint64_t)(regs[i].pci_size_low)); in pci_get_available_prop()
1392 newregs[j].pci_size_low = (uint32_t)dlen; in pci_get_available_prop()
1404 newregs[j].pci_size_low = (uint32_t)dlen; in pci_get_available_prop()
1524 ((uint64_t)(regs[i].pci_size_low)); in pci_put_available_prop()
1605 newregs[j].pci_size_low = (uint32_t)len; in pci_put_available_prop()
[all …]
/titanic_44/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c891 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { in cardbus_bridge_assign()
897 entry, reg[i].pci_size_low, &mem_answer); in cardbus_bridge_assign()
918 entry, reg[i].pci_size_low, &mem_answer); in cardbus_bridge_assign()
955 entry, reg[i].pci_size_low, &io_answer); in cardbus_bridge_assign()
1039 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { in cardbus_isa_bridge_ranges()
1045 entry, reg[i].pci_size_low, &io_answer); in cardbus_isa_bridge_ranges()
1055 range.rng_size = reg[i].pci_size_low; in cardbus_isa_bridge_ranges()
2096 pci_rp[i].pci_size_low + in cardbus_sum_resources()
2098 pci_rp[i].pci_size_low); in cardbus_sum_resources()
2102 pci_rp[i].pci_size_low, in cardbus_sum_resources()
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H A Dcardbus.c836 new_avail_p->pci_size_low = old_avail_p->phys_len; in cardbus_convert_properties()
1087 rn, regs[rn].pci_size_low); in cardbus_ctlops()
1088 *(off_t *)result = regs[rn].pci_size_low; in cardbus_ctlops()
1902 rp->regspec_size = pci_rp->pci_size_low; in pcirp2rp()
/titanic_44/usr/src/uts/sun4u/opl/io/pcicmu/
H A Dpcmu_util.c151 rp->pci_size_hi, rp->pci_size_low); in pcmu_reloc_reg()
180 rp->pci_size_hi, rp->pci_size_low); in pcmu_reloc_reg()
196 uint32_t sz = pcmu_rp->pci_size_low; in pcmu_xlate_reg()
451 size = pcmu_rp[rnumber].pci_size_low | in pcmu_get_reg_set_size()
/titanic_44/usr/src/uts/sun4/io/px/
H A Dpx_util.c153 rp->pci_size_hi, rp->pci_size_low); in px_reloc_reg()
203 rp->pci_size_hi, rp->pci_size_low, i); in px_reloc_reg()
222 reg_sz = (uint64_t)px_rp->pci_size_hi << 32 | px_rp->pci_size_low; in px_xlate_reg()
569 size = pci_rp[rnumber].pci_size_low | in px_get_reg_set_size()
H A Dpx_tools.c483 dev_regspec.pci_size_low = 4; in pxtool_get_phys_addr()
/titanic_44/usr/src/uts/sun4/io/efcode/
H A Dfcpci.c561 p.pci_size_low = len = fc_cell2size(fc_arg(cp, 0)); in pfc_map_in()
852 p.pci_size_hi = p.pci_size_low = 0; in pfc_config_fetch()
984 p.pci_size_hi = p.pci_size_low = 0; in pfc_config_store()
1281 l = phys_spec.pci_size_low; in pci_alloc_resource()
1295 if (assigned[i].pci_size_low >= in pci_alloc_resource()
1296 phys_spec.pci_size_low) { in pci_alloc_resource()
1331 l = MAX(assigned[i].pci_size_low, in pci_alloc_resource()
1332 phys_spec.pci_size_low); in pci_alloc_resource()
1334 phys_spec.pci_size_low = l; in pci_alloc_resource()
1351 config.pci_size_hi = config.pci_size_low = 0; in pci_alloc_resource()
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/titanic_44/usr/src/uts/i86pc/io/pciex/
H A Dnpe.c517 pci_rp->pci_size_low = PCIE_CONF_HDR_SIZE; in npe_bus_map()
532 (uint64_t)pci_rp->pci_size_low; in npe_bus_map()
614 pci_rp->pci_size_low = PCIE_CONF_HDR_SIZE; in npe_bus_map()
629 pci_rlength = (uint64_t)pci_rp->pci_size_low | in npe_bus_map()
756 val = drv_regp[rn].pci_size_low | in npe_ctlops()
/titanic_44/usr/src/uts/intel/io/pci/
H A Dpci_boot.c2471 regs[nreg].pci_size_low = in add_reg_props()
2472 assigned[nasgn].pci_size_low = len; in add_reg_props()
2549 regs[nreg].pci_size_low = in add_reg_props()
2550 assigned[nasgn].pci_size_low = len; in add_reg_props()
2686 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; in add_reg_props()
2708 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; in add_reg_props()
2718 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; in add_reg_props()
2729 regs[nreg].pci_size_low = in add_reg_props()
2730 assigned[nasgn].pci_size_low = 0x20000; in add_reg_props()
2748 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; in add_reg_props()
[all …]
/titanic_44/usr/src/uts/sun4u/io/pci/
H A Dpci_util.c165 rp->pci_size_hi, rp->pci_size_low); in pci_reloc_reg()
203 rp->pci_size_hi, rp->pci_size_low); in pci_reloc_reg()
219 uint32_t sz = pci_rp->pci_size_low; in pci_xlate_reg()
H A Dpci.c526 rp->pci_size_low = len; in pci_map()
1181 size = pci_rp[rnumber].pci_size_low | in get_reg_set_size()
/titanic_44/usr/src/uts/sparc/io/pciex/
H A Dpcieb_sparc.c413 reg_spec[rnum].pci_size_low = addr_spec[anum].pci_size_low; in plx_ro_disable()
/titanic_44/usr/src/uts/sun4u/montecarlo/io/
H A Dacebus.c473 pci_reg.pci_size_low); in acebus_map()
522 rp->pci_size_low = in acebus_apply_range()
988 er[0].rng_size = prp->pci_size_low; in acebus_update_props()
1011 er[1].rng_size = prp->pci_size_low; in acebus_update_props()
/titanic_44/usr/src/uts/i86pc/io/pci/
H A Dpci.c442 (uint64_t)pci_rp->pci_size_low; in pci_bus_map()
490 pci_rlength = (uint64_t)pci_rp->pci_size_low | in pci_bus_map()
588 val = drv_regp[rn].pci_size_low | in pci_ctlops()
/titanic_44/usr/src/uts/intel/io/intel_nhm/
H A Dnhm_pci_cfg.c51 reg.pci_size_low = PCIE_CONF_HDR_SIZE; /* overriden in pciex */ in nhm_pci_cfg_setup()
/titanic_44/usr/src/uts/common/io/drm/
H A Ddrm_memory.c129 regsize = (uint_t)regs[i].pci_size_low; in drm_get_pci_index_reg()
H A Ddrm_pci.c306 (unsigned long)regs[resp->regnum].pci_size_low; in do_get_pci_res()
/titanic_44/usr/src/uts/intel/io/intel_nb5000/
H A Dnb_pci_cfg.c56 reg.pci_size_low = PCIE_CONF_HDR_SIZE; /* overriden in pciex */ in nb_pci_cfg_setup()
/titanic_44/usr/src/uts/common/sys/
H A Dpci.h1150 uint_t pci_size_low; /* low word of size field */ member
/titanic_44/usr/src/uts/i86pc/io/
H A Disa.c451 pci_reg_p->pci_size_low = isa_reg_p->regspec_size; in isa_apply_range()
486 pci_reg_p->pci_size_low = isa_reg_p->regspec_size; in isa_apply_range()
/titanic_44/usr/src/uts/sun4u/io/
H A Dpmubus.c618 pci_regp->pci_size_low = MIN(regp->reg_size, rangep->rng_size); in pmubus_apply_range()
/titanic_44/usr/src/uts/common/os/
H A Dpcifm.c1263 (uint64_t)drv_regp[rn].pci_size_low + in pci_check_regs()
1288 (uint64_t)drv_regp[rn].pci_size_low + in pci_check_regs()

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