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Searched refs:pci_phys_hi (Results 1 – 25 of 64) sorted by relevance

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/titanic_44/usr/src/uts/intel/io/intel_nb5000/
H A Dnb_pci_cfg.c52 reg.pci_phys_hi = 16 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=16, Func=0 */ in nb_pci_cfg_setup()
67 reg.pci_phys_hi += 1 << PCI_REG_FUNC_SHIFT; in nb_pci_cfg_setup()
69 reg.pci_phys_hi = 17 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=17, Func=0 */ in nb_pci_cfg_setup()
79 reg.pci_phys_hi += 1 << PCI_REG_FUNC_SHIFT; in nb_pci_cfg_setup()
81 reg.pci_phys_hi = 21 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=21, Func=0 */ in nb_pci_cfg_setup()
88 reg.pci_phys_hi = 22 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=22, Func=0 */ in nb_pci_cfg_setup()
95 reg.pci_phys_hi = 0; /* Bus=0, Dev=0, Func=0 */ in nb_pci_cfg_setup()
105 reg.pci_phys_hi += 1 << PCI_REG_DEV_SHIFT; in nb_pci_cfg_setup()
/titanic_44/usr/src/uts/sun4/io/efcode/
H A Dfcpci.c563 p.pci_phys_hi = fc_cell2uint(fc_arg(cp, 1)); in pfc_map_in()
850 p.pci_phys_hi = fc_cell2uint(fc_arg(cp, 0)); in pfc_config_fetch()
858 if ((p.pci_phys_hi & PCI_ADDR_MASK) != PCI_ADDR_CONFIG) { in pfc_config_fetch()
860 "invalid config addr: %x\n", p.pci_phys_hi); in pfc_config_fetch()
869 reg = (p.pci_phys_hi & PCI_REG_REG_M) | in pfc_config_fetch()
870 (((p.pci_phys_hi & PCI_REG_EXTREG_M) >> PCI_REG_EXTREG_SHIFT) << 8); in pfc_config_fetch()
872 p.pci_phys_hi &= PCI_BDF_bits; in pfc_config_fetch()
982 p.pci_phys_hi = fc_cell2uint(fc_arg(cp, 0)); in pfc_config_store()
990 if ((p.pci_phys_hi & PCI_ADDR_MASK) != PCI_ADDR_CONFIG) { in pfc_config_store()
992 "invalid config addr: %x\n", p.pci_phys_hi); in pfc_config_store()
[all …]
/titanic_44/usr/src/uts/sun4/io/px/
H A Dpx_util.c148 uint32_t phys_hi = rp->pci_phys_hi; in px_reloc_reg()
152 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low, in px_reloc_reg()
182 uint32_t assign_type = assign_p->pci_phys_hi & PCI_REG_ADDR_M; in px_reloc_reg()
183 uint32_t assign_addr = PCI_REG_BDFR_G(assign_p->pci_phys_hi); in px_reloc_reg()
196 rp->pci_phys_hi ^= PCI_ADDR_MEM64 ^ PCI_ADDR_MEM32; in px_reloc_reg()
202 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low, in px_reloc_reg()
216 uint32_t space_type = PCI_REG_ADDR_G(px_rp->pci_phys_hi); in px_xlate_reg()
228 reg_begin += px_rp->pci_phys_hi << 4; in px_xlate_reg()
351 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi); in px_name_child()
354 PCI_REG_DEV_G(pci_rp[0].pci_phys_hi), func); in px_name_child()
[all …]
/titanic_44/usr/src/uts/intel/io/pciex/
H A Dpcie_nvidia.c228 regs[0].pci_phys_hi = devloc; in add_nvidia_isa_bridge_props()
234 assigned[0].pci_phys_hi = regs[0].pci_phys_hi = (PCI_RELOCAT_B | in add_nvidia_isa_bridge_props()
243 assigned[1].pci_phys_hi = regs[1].pci_phys_hi = (PCI_RELOCAT_B | in add_nvidia_isa_bridge_props()
/titanic_44/usr/src/uts/common/io/
H A Dbusra.c1038 switch (PCI_REG_ADDR_G(regs[i].pci_phys_hi)) { in pci_resource_setup()
1043 (regs[i].pci_phys_hi & PCI_REG_PF_M) ? in pci_resource_setup()
1054 (regs[i].pci_phys_hi & PCI_REG_PF_M) ? in pci_resource_setup()
1071 PCI_REG_ADDR_G(regs[i].pci_phys_hi)); in pci_resource_setup()
1225 if (avail_p->pci_phys_hi == -1u) in pci_resource_setup_avail()
1228 switch (PCI_REG_ADDR_G(avail_p->pci_phys_hi)) { in pci_resource_setup_avail()
1232 (avail_p->pci_phys_hi & PCI_REG_PF_M) ? in pci_resource_setup_avail()
1254 i, avail_p->pci_phys_hi); in pci_resource_setup_avail()
1356 if (type == (regs[i].pci_phys_hi & PCI_ADDR_TYPE_MASK)) { in pci_get_available_prop()
1386 newregs[j].pci_phys_hi = regs[i].pci_phys_hi; in pci_get_available_prop()
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H A Dpci_intr_lib.c841 addr_space = rp->pci_phys_hi & PCI_ADDR_MASK; in pci_msix_init()
842 offset = PCI_REG_REG_G(rp->pci_phys_hi); in pci_msix_init()
890 addr_space = rp->pci_phys_hi & PCI_ADDR_MASK; in pci_msix_init()
891 offset = PCI_REG_REG_G(rp->pci_phys_hi); in pci_msix_init()
/titanic_44/usr/src/uts/sun4u/io/pci/
H A Dpci_util.c161 register uint32_t phys_hi = rp->pci_phys_hi; in pci_reloc_reg()
164 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low, in pci_reloc_reg()
184 uint32_t assign_type = assign_p->pci_phys_hi & PCI_REG_ADDR_M; in pci_reloc_reg()
185 uint32_t assign_addr = PCI_REG_BDFR_G(assign_p->pci_phys_hi); in pci_reloc_reg()
196 rp->pci_phys_hi ^= PCI_ADDR_MEM64 ^ PCI_ADDR_MEM32; in pci_reloc_reg()
202 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low, in pci_reloc_reg()
217 uint32_t space_type = PCI_REG_ADDR_G(pci_rp->pci_phys_hi); in pci_xlate_reg()
227 reg_begin += pci_rp->pci_phys_hi; in pci_xlate_reg()
348 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi); in name_child()
351 PCI_REG_DEV_G(pci_rp[0].pci_phys_hi), func); in name_child()
[all …]
/titanic_44/usr/src/uts/sun4u/opl/io/pcicmu/
H A Dpcmu_util.c144 register uint32_t phys_hi = rp->pci_phys_hi; in pcmu_reloc_reg()
150 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low, in pcmu_reloc_reg()
171 if ((assign_p->pci_phys_hi & mask) == phys_addr) { in pcmu_reloc_reg()
179 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low, in pcmu_reloc_reg()
194 uint32_t space_type = PCI_REG_ADDR_G(pcmu_rp->pci_phys_hi); in pcmu_xlate_reg()
205 reg_begin += pcmu_rp->pci_phys_hi; in pcmu_xlate_reg()
316 func = PCI_REG_FUNC_G(pcmu_rp[0].pci_phys_hi); in name_child()
319 PCI_REG_DEV_G(pcmu_rp[0].pci_phys_hi), func); in name_child()
322 PCI_REG_DEV_G(pcmu_rp[0].pci_phys_hi)); in name_child()
/titanic_44/usr/src/uts/sun4/io/
H A Dpcicfg.c1514 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == in pcicfg_get_ntbridge_child_range()
1520 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == in pcicfg_get_ntbridge_child_range()
1984 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); in pcicfg_bridge_assign()
1986 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { in pcicfg_bridge_assign()
2129 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); in pcicfg_device_assign()
2132 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { in pcicfg_device_assign()
2162 reg[i].pci_phys_hi ^= in pcicfg_device_assign()
2299 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { in pcicfg_device_assign_readonly()
2651 switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) { in pcicfg_sum_resources()
2764 switch (PCI_REG_ADDR_G(pci_ap[i].pci_phys_hi)) { in pcicfg_find_resource_end()
[all …]
/titanic_44/usr/src/uts/sun4u/montecarlo/io/
H A Dacebus.c348 rangep[i].ebus_phys_low, rangep[i].pci_phys_hi, in acebus_get_ranges_prop()
465 pci_reg.pci_phys_hi |= PCI_RELOCAT_B; in acebus_map()
469 pci_reg.pci_phys_hi, in acebus_map()
516 rp->pci_phys_hi = in acebus_apply_range()
517 rangep->pci_phys_hi; in acebus_apply_range()
531 rangep->pci_phys_hi, in acebus_apply_range()
973 if (PCI_REG_REG_G(prp->pci_phys_hi) == er[0].ebus_phys_hi) { in acebus_update_props()
985 er[0].pci_phys_hi = prp->pci_phys_hi; in acebus_update_props()
997 if (PCI_REG_REG_G(prp->pci_phys_hi) == er[1].ebus_phys_hi) { in acebus_update_props()
1008 er[1].pci_phys_hi = prp->pci_phys_hi; in acebus_update_props()
/titanic_44/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c1415 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == in pcicfg_get_ntbridge_child_range()
1420 } else if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == in pcicfg_get_ntbridge_child_range()
1425 } else if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == in pcicfg_get_ntbridge_child_range()
1880 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); in pcicfg_bridge_assign()
1882 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { in pcicfg_bridge_assign()
1885 if (reg[i].pci_phys_hi & PCI_REG_PF_M) { in pcicfg_bridge_assign()
1900 reg[i].pci_phys_hi |= PCI_REG_REL_M; in pcicfg_bridge_assign()
1906 if (reg[i].pci_phys_hi & PCI_REG_PF_M) { in pcicfg_bridge_assign()
1922 reg[i].pci_phys_hi |= PCI_REG_REL_M; in pcicfg_bridge_assign()
1936 reg[i].pci_phys_hi |= PCI_REG_REL_M; in pcicfg_bridge_assign()
[all …]
/titanic_44/usr/src/uts/sparc/io/pciex/
H A Dpcieb_sparc.c105 PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); in pcieb_plat_intr_ops()
383 if ((reg_spec[rnum].pci_phys_hi & PCI_ADDR_MASK) == in plx_ro_disable()
395 if ((addr_spec[anum].pci_phys_hi & PCI_ADDR_MASK) == in plx_ro_disable()
408 reg_spec[rnum].pci_phys_hi = (addr_spec[anum].pci_phys_hi & in plx_ro_disable()
/titanic_44/usr/src/uts/common/io/scsi/adapters/smrt/
H A Dsmrt_device.c33 unsigned type = regs[i].pci_phys_hi & PCI_ADDR_MASK; in smrt_locate_bar()
75 unsigned type = regs[i].pci_phys_hi & PCI_ADDR_MASK; in smrt_locate_cfgtbl()
76 unsigned bar = PCI_REG_REG_G(regs[i].pci_phys_hi); in smrt_locate_cfgtbl()
/titanic_44/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c892 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); in cardbus_bridge_assign()
893 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { in cardbus_bridge_assign()
1040 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { in cardbus_isa_bridge_ranges()
1051 range.par_phys_hi = reg[i].pci_phys_hi | in cardbus_isa_bridge_ranges()
2092 switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) { in cardbus_sum_resources()
2103 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); in cardbus_sum_resources()
2121 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); in cardbus_sum_resources()
2135 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); in cardbus_sum_resources()
2280 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { in cardbus_free_device_resources()
2287 PCI_REG_REG_G(assigned[i].pci_phys_hi)); in cardbus_free_device_resources()
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H A Dcardbus_hp.c891 if (pci_rp->pci_phys_hi == 0) in cbus_configure()
895 bus = PCI_REG_BUS_G(pci_rp->pci_phys_hi); in cbus_configure()
896 device = PCI_REG_DEV_G(pci_rp->pci_phys_hi); in cbus_configure()
897 function = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); in cbus_configure()
991 if (pci_rp->pci_phys_hi == 0) in cbus_unconfigure()
994 bus = PCI_REG_BUS_G(pci_rp->pci_phys_hi); in cbus_unconfigure()
999 device = PCI_REG_DEV_G(pci_rp->pci_phys_hi); in cbus_unconfigure()
1000 func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); in cbus_unconfigure()
H A Dcardbus.c832 new_avail_p->pci_phys_hi = old_avail_p->phys_hi; in cardbus_convert_properties()
1001 if (pci_rp->pci_phys_hi == 0) in cardbus_ctlops()
1011 bus = PCI_REG_BUS_G(pci_rp->pci_phys_hi); in cardbus_ctlops()
1012 device = PCI_REG_DEV_G(pci_rp->pci_phys_hi); in cardbus_ctlops()
1013 function = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); in cardbus_ctlops()
1342 bus = PCI_REG_BUS_G(pci_rp->pci_phys_hi); in cardbus_name_child()
1343 device = PCI_REG_DEV_G(pci_rp->pci_phys_hi); in cardbus_name_child()
1344 func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); in cardbus_name_child()
1893 if (PCI_REG_ADDR_G(pci_rp->pci_phys_hi) == in pcirp2rp()
/titanic_44/usr/src/uts/i86pc/io/gfx_private/
H A Dgfxp_pci.c101 *bus = PCI_REG_BUS_G(pci_rp->pci_phys_hi); in gfxp_pci_get_bsf()
102 *dev = PCI_REG_DEV_G(pci_rp->pci_phys_hi); in gfxp_pci_get_bsf()
103 *func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); in gfxp_pci_get_bsf()
/titanic_44/usr/src/uts/intel/io/pci/
H A Dpci_boot.c2385 regs[0].pci_phys_hi = devloc; in add_reg_props()
2465 regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc | in add_reg_props()
2469 assigned[nasgn].pci_phys_hi = in add_reg_props()
2470 PCI_RELOCAT_B | regs[nreg].pci_phys_hi; in add_reg_props()
2582 regs[nreg].pci_phys_hi = in add_reg_props()
2583 assigned[nasgn].pci_phys_hi = phys_hi; in add_reg_props()
2584 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; in add_reg_props()
2680 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; in add_reg_props()
2681 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | in add_reg_props()
2705 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = in add_reg_props()
[all …]
/titanic_44/usr/src/uts/i86pc/io/pci/
H A Dpci.c415 space = pci_rp->pci_phys_hi & PCI_REG_ADDR_M; in pci_bus_map()
479 cfp->c_busnum = PCI_REG_BUS_G(pci_rp->pci_phys_hi); in pci_bus_map()
480 cfp->c_devnum = PCI_REG_DEV_G(pci_rp->pci_phys_hi); in pci_bus_map()
481 cfp->c_funcnum = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); in pci_bus_map()
/titanic_44/usr/src/uts/common/io/fibre-channel/fca/oce/
H A Doce_hw.c204 dev->pci_bus = PCI_REG_BUS_G(pci_rp->pci_phys_hi); in oce_get_bdf()
205 dev->pci_device = PCI_REG_DEV_G(pci_rp->pci_phys_hi); in oce_get_bdf()
206 dev->pci_function = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); in oce_get_bdf()
/titanic_44/usr/src/uts/i86pc/io/pciex/
H A Dnpe.c488 space = pci_rp->pci_phys_hi & PCI_REG_ADDR_M; in npe_bus_map()
578 cfp->c_busnum = PCI_REG_BUS_G(pci_rp->pci_phys_hi); in npe_bus_map()
579 cfp->c_devnum = PCI_REG_DEV_G(pci_rp->pci_phys_hi); in npe_bus_map()
580 cfp->c_funcnum = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); in npe_bus_map()
/titanic_44/usr/src/uts/common/io/pciex/hotplug/
H A Dpcie_hp.c1057 pci_dev = PCI_REG_DEV_G(pci_rp->pci_phys_hi); in pcie_hp_match_dev_func()
1058 pci_func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); in pcie_hp_match_dev_func()
1094 pci_dev = PCI_REG_DEV_G(pci_rp->pci_phys_hi); in pcie_hp_match_dev()
1141 pci_dev = PCI_REG_DEV_G(pci_rp->pci_phys_hi); in pcie_hp_list_occupants()
/titanic_44/usr/src/uts/sun4u/io/
H A Dpmubus.c614 pci_regp->pci_phys_hi = rangep->rng_parent_hi; in pmubus_apply_range()
621 if (pci_regp->pci_phys_hi == pmubusp->pmubus_regp->pci_phys_hi) { in pmubus_apply_range()
/titanic_44/usr/src/uts/common/os/
H A Dpcifm.c456 phys_hi = pci_rp->pci_phys_hi; in pci_ereport_setup()
1230 PCI_REG_ADDR_G(drv_regp[rn].pci_phys_hi) && in pci_check_regs()
1233 (drv_regp[rn].pci_phys_hi & (PCI_REG_BUS_M | in pci_check_regs()
1253 if ((drv_regp[rn].pci_phys_hi & PCI_RELOCAT_B) && in pci_check_regs()
1256 PCI_REG_ADDR_G(drv_regp[rn].pci_phys_hi)) && in pci_check_regs()
1281 PCI_REG_ADDR_G(drv_regp[rn].pci_phys_hi)) && in pci_check_regs()
/titanic_44/usr/src/uts/intel/io/intel_nhm/
H A Dnhm_pci_cfg.c55 reg.pci_phys_hi = ((SOCKET_BUS(i)) in nhm_pci_cfg_setup()

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