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Searched refs:pci_config_put32 (Results 1 – 25 of 57) sorted by relevance

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/titanic_44/usr/src/uts/intel/io/dktp/controller/ata/
H A Dsil3xxx.h82 pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \
83 pci_config_put32(handle, PCI_CONF_BA5_IND_ACCESS, value); \
88 pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \
/titanic_44/usr/src/uts/intel/io/agpgart/
H A Damd64_gart.c96 pci_config_put32(sc->gsoft_pcihdl, AMD64_GART_CACHE_CTL, value); in amd64_invalidate_gtlb()
126 pci_config_put32(sc->gsoft_pcihdl, AMD64_APERTURE_CONTROL, aper_ctl); in amd64_enable_gart()
288 pci_config_put32(sc->gsoft_pcihdl, AMD64_GART_BASE, addr); in amd64_gart_ioctl()
307 pci_config_put32(sc->gsoft_pcihdl, AMD64_GART_BASE, 0x00000000); in amd64_gart_ioctl()
H A Dagptarget.c304 pci_config_put32(softstate->tsoft_pcihdl, in agp_target_set_gartaddr()
743 pci_config_put32(st->tsoft_pcihdl, in agp_target_ioctl()
811 pci_config_put32(st->tsoft_pcihdl, in agp_target_ioctl()
815 pci_config_put32(st->tsoft_pcihdl, in agp_target_ioctl()
/titanic_44/usr/src/uts/common/os/
H A Dsunpci.c127 pci_config_put32(ddi_acc_handle_t handle, off_t offset, uint32_t value) in pci_config_put32() function
791 pci_config_put32(confhdl, offset, *regbuf);
835 pci_config_put32(confhdl, offset, *p);
873 pci_config_put32(confhdl, PCI_CONF_BASE0, chs_p->chs_base0);
874 pci_config_put32(confhdl, PCI_CONF_BASE1, chs_p->chs_base1);
875 pci_config_put32(confhdl, PCI_CONF_BASE2, chs_p->chs_base2);
876 pci_config_put32(confhdl, PCI_CONF_BASE3, chs_p->chs_base3);
877 pci_config_put32(confhdl, PCI_CONF_BASE4, chs_p->chs_base4);
878 pci_config_put32(confhdl, PCI_CONF_BASE5, chs_p->chs_base5);
H A Dpcifm.c161 pci_config_put32(erpt_p->pe_hdl, in pcix_regs_gather()
252 pci_config_put32(erpt_p->pe_hdl, in pcix_regs_clear()
266 pci_config_put32(erpt_p->pe_hdl, in pcix_regs_clear()
271 pci_config_put32(erpt_p->pe_hdl, in pcix_regs_clear()
288 pci_config_put32(erpt_p->pe_hdl, in pcix_regs_clear()
300 pci_config_put32(erpt_p->pe_hdl, in pcix_regs_clear()
/titanic_44/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c899 pci_config_put32(handle, offset, in cardbus_bridge_assign()
901 pci_config_put32(handle, offset + 4, in cardbus_bridge_assign()
919 pci_config_put32(handle, offset, 0xffffffff); in cardbus_bridge_assign()
922 pci_config_put32(handle, offset, in cardbus_bridge_assign()
935 pci_config_put32(handle, in cardbus_bridge_assign()
956 pci_config_put32(handle, offset, io_answer); in cardbus_bridge_assign()
1141 pci_config_put32(phdl->handle, phdl->io_decode_reg, io_reg); in cardbus_add_isa_reg()
1443 pci_config_put32(handle, PCI_BCNF_PF_BASE_LOW, 0x0000ffff); in cardbus_setup_bridge()
1444 pci_config_put32(handle, PCI_BCNF_PF_BASE_HIGH, 0xffffffff); in cardbus_setup_bridge()
1446 pci_config_put32(handle, PCI_BCNF_PF_LIMIT_HIGH, 0x0); in cardbus_setup_bridge()
[all …]
/titanic_44/usr/src/uts/sun4u/io/pci/
H A Ddb21554.c1037 pci_config_put32(dbp->conf_handle, in db_enable_io()
1050 pci_config_put32(dbp->conf_handle, (off_t)DB_CONF_DS_IO_MEM1_TR_BASE, in db_enable_io()
1054 pci_config_put32(dbp->conf_handle, (off_t)DB_CONF_DS_MEM2_TR_BASE, in db_enable_io()
1058 pci_config_put32(dbp->conf_handle, (off_t)DB_CONF_DS_MEM3_TR_BASE, in db_enable_io()
1062 pci_config_put32(dbp->conf_handle, (off_t)DB_CONF_US_IO_MEM0_TR_BASE, in db_enable_io()
1066 pci_config_put32(dbp->conf_handle, (off_t)DB_CONF_US_MEM1_TR_BASE, in db_enable_io()
1286 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
1296 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
1299 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
1308 pci_config_put32(dbp->conf_handle, in db_set_dvma_range()
[all …]
/titanic_44/usr/src/uts/common/io/bge/
H A Dbge_chip2.c215 pci_config_put32(bgep->cfg_handle, regno, regval); in bge_cfg_clr32()
250 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); in bge_ind_get32()
277 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); in bge_ind_put32()
278 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); in bge_ind_put32()
370 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0); in bge_chip_cfg_init()
483 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); in bge_chip_cfg_init()
495 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PCISTATE, pci_state); in bge_chip_cfg_init()
554 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); in bge_chip_cfg_init()
555 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); in bge_chip_cfg_init()
894 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); in bge_nic_setwin()
[all …]
/titanic_44/usr/src/uts/intel/io/mc-amd/
H A Dmcamd_pcicfg.c92 pci_config_put32(hdlp->cfh_hdl, offset, val); in mc_pcicfg_put32()
/titanic_44/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c1916 pci_config_put32(handle, offset, in pcicfg_bridge_assign()
1931 pci_config_put32(handle, offset, io_answer); in pcicfg_bridge_assign()
2062 pci_config_put32(handle, offset, in pcicfg_device_assign()
2065 pci_config_put32(handle, offset + 4, in pcicfg_device_assign()
2100 pci_config_put32(handle, offset, in pcicfg_device_assign()
2127 pci_config_put32(handle, offset, in pcicfg_device_assign()
3583 pci_config_put32(handle, PCI_BCNF_PF_BASE_HIGH, in pcicfg_setup_bridge()
3640 pci_config_put32(handle, PCI_BCNF_PF_LIMIT_HIGH, PCICFG_HIADDR( in pcicfg_update_bridge()
3860 pci_config_put32(config_handle, i, 0xffffffff); in pcicfg_populate_reg_props()
3901 pci_config_put32(config_handle, PCI_CONF_ROM, 0xfffffffe); in pcicfg_populate_reg_props()
[all …]
/titanic_44/usr/src/uts/intel/io/amr/
H A Damrreg.h638 #define AMR_QPUT_IDB(sc, val) pci_config_put32(sc->regsmap_handle, \
642 #define AMR_QPUT_ODB(sc, val) pci_config_put32(sc->regsmap_handle, \
/titanic_44/usr/src/uts/i86pc/io/pcplusmp/
H A Dapic_introp.c115 pci_config_put32(handle, in apic_pci_msi_enable_vector()
119 pci_config_put32(handle, in apic_pci_msi_enable_vector()
595 pci_config_put32(handle, msi_mask_off, (uint32_t)-1); in apic_grp_set_cpu()
626 pci_config_put32(handle, msi_mask_off, msi_pvm); in apic_grp_set_cpu()
/titanic_44/usr/src/uts/common/io/chxge/
H A Dch.c483 pci_config_put32(chp->ch_hpci, 0x44, 3); in ch_attach()
484 pci_config_put32(chp->ch_hpci, 0x44, 0); in ch_attach()
752 pci_config_put32(chp->ch_hpci, 0x44, 3); in ch_quiesce()
753 pci_config_put32(chp->ch_hpci, 0x44, 0); in ch_quiesce()
812 pci_config_put32(chp->ch_hpci, 0x44, 3); in ch_detach()
813 pci_config_put32(chp->ch_hpci, 0x44, 0); in ch_detach()
1431 pci_config_put32(chp->ch_hpci, 0x44, 3); in ch_reset()
1432 pci_config_put32(chp->ch_hpci, 0x44, 0); in ch_reset()
H A Dglue.c125 pci_config_put32(obj->ch_hpci, reg, val); in t1_os_pci_write_config_4()
282 pci_config_put32(chp->ch_hpci, pe->addr, pe->pe_reg_val); in pe_ioctl()
/titanic_44/usr/src/uts/common/io/cxgbe/t4nex/
H A Dadapter.c72 pci_config_put32(sc->pci_regh, reg, val); in t4_os_pci_write_cfg4()
/titanic_44/usr/src/uts/sun4/io/
H A Dpcicfg.c2010 pci_config_put32(handle, in pcicfg_bridge_assign()
2025 pci_config_put32(handle, offset, io_answer); in pcicfg_bridge_assign()
2150 pci_config_put32(handle, in pcicfg_device_assign()
2154 pci_config_put32(handle, offset + 4, in pcicfg_device_assign()
2183 pci_config_put32(handle, in pcicfg_device_assign()
2205 pci_config_put32(handle, in pcicfg_device_assign()
3869 pci_config_put32(handle, PCI_BCNF_PF_BASE_LOW, 0x0000ffff); in pcicfg_setup_bridge()
3870 pci_config_put32(handle, PCI_BCNF_PF_BASE_HIGH, 0xffffffff); in pcicfg_setup_bridge()
3871 pci_config_put32(handle, PCI_BCNF_PF_LIMIT_HIGH, 0x0); in pcicfg_setup_bridge()
4206 pci_config_put32(config_handle, i, 0xffffffff); in pcicfg_populate_reg_props()
[all …]
/titanic_44/usr/src/uts/intel/io/pciex/
H A Dpcieb_x86.c502 pci_config_put32(cfg_hdl, reg->offset, value); in pcieb_intel_serr_workaround()
599 pci_config_put32(bus_p->bus_cfg_hdl, in pcieb_intel_mps_workaround()
/titanic_44/usr/src/uts/common/io/e1000g/
H A De1000g_debug.c581 pci_config_put32(handle, offset, 0xffffffff); in pciconfig_bar()
589 pci_config_put32(handle, offset, base); in pciconfig_bar()
/titanic_44/usr/src/uts/common/io/
H A Dpci_cap.c314 pci_config_put32(h, offset, data); in pci_cap_put()
/titanic_44/usr/src/uts/sun4u/io/
H A Dpmubus.c561 pci_config_put32(softsp->pmubus_reghdl, offset, tmp); in pmubus_put32()
569 pci_config_put32(softsp->pmubus_reghdl, offset, value); in pmubus_put32()
/titanic_44/usr/src/uts/common/io/1394/adapters/
H A Dhci1394_attach.c591 pci_config_put32(soft_state->pci_config, in hci1394_pci_init()
681 pci_config_put32(soft_state->pci_config, in hci1394_pci_resume()
/titanic_44/usr/src/uts/common/io/yge/
H A Dyge.c602 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, val); in yge_phy_power()
613 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0); in yge_phy_power()
619 pci_config_put32(dev->d_pcih, PCI_OUR_REG_4, our); in yge_phy_power()
624 pci_config_put32(dev->d_pcih, PCI_OUR_REG_5, our); in yge_phy_power()
626 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, 0); in yge_phy_power()
660 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, val); in yge_phy_power()
747 pci_config_put32(pcih, PCI_OUR_REG_1, val); in yge_reset()
1222 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0); in yge_attach()
1771 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0); in yge_resume()
/titanic_44/usr/src/uts/common/io/ib/adapters/hermon/
H A Dhermon.c3911 pci_config_put32(hdl, i << 2, state->hs_cfg_data[i]); in hermon_sw_reset()
3921 pci_config_put32(hdl, offset + HERMON_PCI_CAP_DEV_OFFS, data32); in hermon_sw_reset()
3923 pci_config_put32(hdl, offset + HERMON_PCI_CAP_LNK_OFFS, data32); in hermon_sw_reset()
3925 pci_config_put32(hdl, 0x04, (state->hs_cfg_data[1] | 0x0006)); in hermon_sw_reset()
4193 (void) pci_config_put32(hdl, offset, addr << 16); in hermon_pci_read_vpd()
4968 pci_config_put32(pcihdl, i << 2, state->hs_cfg_data[i]); in hermon_quiesce()
5001 pci_config_put32(pcihdl, offset + HERMON_PCI_CAP_DEV_OFFS, data32); in hermon_quiesce()
5003 pci_config_put32(pcihdl, offset + HERMON_PCI_CAP_LNK_OFFS, data32); in hermon_quiesce()
5006 pci_config_put32(pcihdl, 0x04, (state->hs_cfg_data[1] | 0x0006)); in hermon_quiesce()
/titanic_44/usr/src/uts/common/io/nge/
H A Dnge_chip.c170 pci_config_put32(ngep->cfg_handle, regno, regval); in nge_chip_poke_cfg()
630 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, in nge_chip_cfg_init()
647 pci_config_put32(handle, PCI_CONF_HT_MSI_MASK, in nge_chip_cfg_init()
654 pci_config_put32(handle, PCI_CONF_HT_MSI_MAP_CAP, in nge_chip_cfg_init()
661 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, in nge_chip_cfg_init()
/titanic_44/usr/src/uts/common/io/xge/drv/
H A Dxge_osdep.h314 pci_config_put32(cfgh, where, val)

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