| /titanic_44/usr/src/uts/i86xpv/io/psm/ |
| H A D | xpv_intr.c | 270 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_enable_vector()
293 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_disable_mode()
299 pci_config_put16(handle, cap_ptr + PCI_MSIX_CTRL, in apic_pci_msi_disable_mode()
324 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_enable_mode()
347 pci_config_put16(handle, cap_ptr + PCI_MSIX_CTRL, in apic_pci_msi_enable_mode()
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| /titanic_44/usr/src/uts/common/io/igb/ |
| H A D | igb_osdep.c | 51 pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value); in e1000_write_pci_cfg()
102 pci_config_put16(OS_DEP(hw)->cfg_handle, in e1000_write_pcie_cap_reg()
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| /titanic_44/usr/src/uts/common/io/e1000g/ |
| H A D | e1000g_osdep.c | 48 pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value); in e1000_write_pci_cfg()
134 pci_config_put16(OS_DEP(hw)->cfg_handle, in e1000_write_pcie_cap_reg()
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| H A D | e1000g_debug.c | 578 pci_config_put16(handle, PCI_CONF_COMM, (comm & ~bits_comm)); in pciconfig_bar()
592 pci_config_put16(handle, PCI_CONF_COMM, comm); in pciconfig_bar()
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| /titanic_44/usr/src/uts/intel/io/hotplug/pcicfg/ |
| H A D | pcicfg.c | 3167 pci_config_put16(config_handle, PCI_CONF_COMM, in pcicfg_device_on()
3177 pci_config_put16(config_handle, PCI_CONF_COMM, 0x0); in pcicfg_device_off()
3555 pci_config_put16(handle, PCI_BCNF_BCNTRL, in pcicfg_setup_bridge()
3558 pci_config_put16(handle, PCI_BCNF_BCNTRL, in pcicfg_setup_bridge()
3566 pci_config_put16(handle, PCI_BCNF_MEM_BASE, in pcicfg_setup_bridge()
3574 pci_config_put16(handle, PCI_BCNF_IO_BASE_HI, in pcicfg_setup_bridge()
3581 pci_config_put16(handle, PCI_BCNF_PF_BASE_LOW, in pcicfg_setup_bridge()
3589 pci_config_put16(handle, PCI_BCNF_SEC_STATUS, 0xffff); in pcicfg_setup_bridge()
3616 pci_config_put16(handle, PCI_BCNF_MEM_LIMIT, in pcicfg_update_bridge()
3637 pci_config_put16(handle, PCI_BCNF_PF_LIMIT_LOW, in pcicfg_update_bridge()
[all …]
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| /titanic_44/usr/src/uts/sun4u/io/pci/ |
| H A D | simba.c | 432 pci_config_put16(simba->config_handle, 0x6, 0xffff); in simba_attach()
433 pci_config_put16(simba->config_handle, 0x1e, 0xffff); in simba_attach()
791 pci_config_put16(config_handle, PCI_CONF_COMM, command); in simba_initchild()
794 pci_config_put16(config_handle, PCI_CONF_STAT, 0xffff); in simba_initchild()
1014 pci_config_put16(ch, PCI_CONF_COMM, statep->command); in simba_restore_config_regs()
1016 pci_config_put16(ch, PCI_BCNF_BCNTRL, in simba_restore_config_regs()
1029 pci_config_put16(ch, PCI_BCNF_BCNTRL, in simba_restore_config_regs()
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| /titanic_44/usr/src/uts/sun4/io/ |
| H A D | pcicfg.c | 3388 pci_config_put16(config_handle, PCI_CONF_COMM, in pcicfg_device_on()
3398 pci_config_put16(config_handle, PCI_CONF_COMM, 0x0); in pcicfg_device_off()
3838 pci_config_put16(handle, PCI_BCNF_BCNTRL, in pcicfg_setup_bridge()
3843 pci_config_put16(handle, PCI_BCNF_BCNTRL, in pcicfg_setup_bridge()
3850 pci_config_put16(handle, PCI_BCNF_MEM_BASE, in pcicfg_setup_bridge()
3858 pci_config_put16(handle, PCI_BCNF_IO_BASE_HI, in pcicfg_setup_bridge()
3864 pci_config_put16(handle, PCI_BCNF_SEC_STATUS, 0xffff); in pcicfg_setup_bridge()
3901 pci_config_put16(handle, PCI_BCNF_MEM_LIMIT, in pcicfg_update_bridge()
3925 pci_config_put16(handle, PCI_BCNF_IO_LIMIT_HI, in pcicfg_update_bridge()
3953 pci_config_put16(h, PCI_CONF_COMM, val); in pcicfg_disable_bridge_probe_err()
[all …]
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| /titanic_44/usr/src/uts/common/io/ixgbe/ |
| H A D | ixgbe_osdep.c | 41 pci_config_put16(OS_DEP(hw)->cfg_handle, reg, val); in ixgbe_write_pci_cfg()
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| /titanic_44/usr/src/uts/intel/io/agpgart/ |
| H A D | agptarget.c | 301 pci_config_put16(softstate->tsoft_pcihdl, in agp_target_set_gartaddr()
498 pci_config_put16(softstate->tsoft_pcihdl, in intel_br_resume()
758 pci_config_put16(st->tsoft_pcihdl, in agp_target_ioctl()
761 pci_config_put16(st->tsoft_pcihdl, in agp_target_ioctl()
797 pci_config_put16(st->tsoft_pcihdl, in agp_target_ioctl()
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| /titanic_44/usr/src/uts/common/io/cardbus/ |
| H A D | cardbus_cfg.c | 1409 pci_config_put16(handle, PCI_BCNF_MEM_BASE, in cardbus_setup_bridge()
1432 pci_config_put16(handle, PCI_BCNF_IO_BASE_HI, in cardbus_setup_bridge()
1438 pci_config_put16(handle, PCI_BCNF_SEC_STATUS, 0xffff); in cardbus_setup_bridge()
1505 pci_config_put16(handle, PCI_CBUS_SEC_STATUS, 0xffff); in cardbus_setup_bridge()
1617 pci_config_put16(handle, PCI_BCNF_MEM_LIMIT, in cardbus_update_bridge()
1684 pci_config_put16(handle, PCI_BCNF_IO_LIMIT_HI, in cardbus_update_bridge()
1690 pci_config_put16(handle, PCI_CONF_COMM, word16); in cardbus_update_bridge()
4013 pci_config_put16(config_handle, PCI_CONF_COMM, comm);
4043 pci_config_put16(config_handle, PCI_CONF_COMM, comm);
4049 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL,
[all …]
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| /titanic_44/usr/src/uts/common/os/ |
| H A D | sunpci.c | 116 pci_config_put16(ddi_acc_handle_t handle, off_t offset, uint16_t value) in pci_config_put16() function
857 pci_config_put16(confhdl, PCI_CONF_COMM,
861 pci_config_put16(confhdl, PCI_BCNF_BCNTRL,
1110 pci_config_put16(hdl, PCI_CONF_COMM, pcicmd);
1143 pci_config_put16(hdl, p->ppc_cap_offset + PCI_PMCSR,
1145 pci_config_put16(hdl, p->ppc_cap_offset + PCI_PMCSR,
1211 pci_config_put16(hdl, pmcap + PCI_PMCSR, pmcsr);
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| H A D | pcifm.c | 247 pci_config_put16(erpt_p->pe_hdl, in pcix_regs_clear()
319 pci_config_put16(erpt_p->pe_hdl, PCI_CONF_STAT, in pci_regs_clear()
327 pci_config_put16(erpt_p->pe_hdl, PCI_BCNF_SEC_STATUS, in pci_regs_clear()
332 pci_config_put16(erpt_p->pe_hdl, PCI_BCNF_BCNTRL, in pci_regs_clear()
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| /titanic_44/usr/src/uts/i86pc/io/pciex/ |
| H A D | npe_misc.c | 127 (void) pci_config_put16(cfg_hdl, in npe_ck804_fix_aer_ptr()
288 pci_config_put16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF, reg); in npe_enable_htmsi()
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| /titanic_44/usr/src/uts/i86pc/io/pcplusmp/ |
| H A D | apic_introp.c | 110 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_enable_vector()
121 pci_config_put16(handle, in apic_pci_msi_enable_vector()
124 pci_config_put16(handle, in apic_pci_msi_enable_vector()
424 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_enable_mode()
447 pci_config_put16(handle, cap_ptr + PCI_MSIX_CTRL, in apic_pci_msi_enable_mode()
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| H A D | apic_common.c | 1658 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_unconfigure()
1662 pci_config_put16(handle, in apic_pci_msi_unconfigure()
1667 pci_config_put16(handle, in apic_pci_msi_unconfigure()
1715 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apic_pci_msi_disable_mode()
1721 pci_config_put16(handle, cap_ptr + PCI_MSIX_CTRL, in apic_pci_msi_disable_mode()
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| /titanic_44/usr/src/uts/common/io/cxgbe/t4nex/ |
| H A D | adapter.c | 60 pci_config_put16(sc->pci_regh, reg, val); in t4_os_pci_write_cfg2()
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| /titanic_44/usr/src/uts/sparc/io/pciex/ |
| H A D | pcieb_sparc.c | 240 pci_config_put16(config_handle, PCI_BCNF_PRIBUS, bus_num); in pcieb_attach_plx_workarounds()
255 pci_config_put16(config_handle, PCI_CONF_COMM, in pcieb_attach_plx_workarounds()
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| /titanic_44/usr/src/uts/intel/io/pciex/ |
| H A D | pcieb_x86.c | 512 pci_config_put16(cfg_hdl, reg->offset, in pcieb_intel_serr_workaround()
630 pci_config_put16(cfg_hdl, PCI_CONF_COMM, in pcieb_intel_sw_workaround()
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| /titanic_44/usr/src/uts/common/io/ |
| H A D | pci_intr_lib.c | 1035 pci_config_put16(cfg_hdl, PCI_CONF_COMM, cmdreg); in pci_intx_get_cap()
1058 pci_config_put16(cfg_hdl, PCI_CONF_COMM, savereg); in pci_intx_get_cap()
1091 pci_config_put16(cfg_hdl, PCI_CONF_COMM, cmdreg); in pci_intx_clr_mask()
1123 pci_config_put16(cfg_hdl, PCI_CONF_COMM, cmdreg); in pci_intx_set_mask()
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| H A D | pci_cap.c | 311 pci_config_put16(h, offset, data); in pci_cap_put()
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| /titanic_44/usr/src/uts/intel/io/pci/ |
| H A D | pci_pci.c | 720 pci_config_put16(config_handle, PCI_CONF_COMM, command); in ppb_initchild()
817 pci_config_put16(config_handle, PCI_CONF_COMM, in ppb_restore_config_regs()
859 pci_config_put16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF, reg); in ppb_ht_msimap_set()
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| /titanic_44/usr/src/uts/common/io/i40e/ |
| H A D | i40e_osdep.h | 162 (pci_config_put16(OS_DEP(hw)->ios_cfg_handle, (reg), (value)))
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| /titanic_44/usr/src/uts/common/io/audio/drv/audiosolo/ |
| H A D | audiosolo.c | 1204 pci_config_put16(dev->pcih, ESS_PCI_LEGACYCONTROL, 0x8041); in solo_init_hw()
1212 pci_config_put16(dev->pcih, ESS_PCI_DDMACONTROL, data & 0xffff); in solo_init_hw()
1218 pci_config_put16(dev->pcih, ESS_PCI_CONFIG, 0); in solo_init_hw()
1389 pci_config_put16(dev->pcih, PCI_CONF_COMM, data); in solo_attach()
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| /titanic_44/usr/src/uts/common/io/yge/ |
| H A D | yge.c | 718 pci_config_put16(pcih, PCI_CONF_STAT, status); in yge_reset()
737 pci_config_put16(pcih, PCI_CONF_CACHE_LINESZ, 2); in yge_reset()
742 pci_config_put16(pcih, PCI_CONF_CACHE_LINESZ, 2); in yge_reset()
834 pci_config_put16(pcih, pcix + 2, pcix_cmd); in yge_reset()
845 pci_config_put16(pcih, PEX_DEV_CTRL, v); in yge_reset()
1201 pci_config_put16(dev->d_pcih, pm_cap + PCI_PMCSR, in yge_attach()
1206 pci_config_put16(dev->d_pcih, PCI_CONF_COMM, in yge_attach()
1757 pci_config_put16(dev->d_pcih, pm_cap + PCI_PMCSR, in yge_resume()
1762 pci_config_put16(dev->d_pcih, PCI_CONF_COMM, in yge_resume()
2118 pci_config_put16(dev->d_pcih, PCI_CONF_STAT, v16 | in yge_intr_hwerr()
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| /titanic_44/usr/src/uts/i86pc/io/apix/ |
| H A D | apix_utils.c | 294 pci_config_put16((_hdl), (_cap) + PCI_MSI_64BIT_DATA, (_v));\
296 pci_config_put16((_hdl), (_cap) + PCI_MSI_32BIT_DATA, (_v));\
345 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apix_pci_msi_enable_vector()
391 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); in apix_pci_msi_enable_mode()
412 pci_config_put16(handle, cap_ptr + PCI_MSIX_CTRL, in apix_pci_msi_enable_mode()
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